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    EFFECTIVE GATE LENGTH CIRCUIT MODELING BASED ON CONCURRENT LENGTH AND MOBILITY ANALYSIS
    1.
    发明申请
    EFFECTIVE GATE LENGTH CIRCUIT MODELING BASED ON CONCURRENT LENGTH AND MOBILITY ANALYSIS 有权
    基于同期长度和移动性分析的有效门限长度电路建模

    公开(公告)号：US20100257493A1

    公开(公告)日：2010-10-07

    申请号：US12416222

    申请日：2009-04-01

    申请人： Kanak B. Agarwal ,  Vivek Joshi

    发明人： Kanak B. Agarwal ,  Vivek Joshi

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036

    摘要： Disclosed is a computer implemented method and computer program product to determine metal oxide semiconductor (MOS) gate functional limitations. A simulator obtains a plurality of slices of a MOS gate, the slices each comprising at least one parameter, the parameter comprising a slice gate width and a slice gate length. The simulator determines a current for each slice based on a slice gate length of the slice to form a length-based current for each slice. The simulator determines a length-based current for the MOS gate by summing the length-based current for each slice. The simulator calculates a stress profile for each slice. The simulator determines a slice carrier mobility for each slice based on the stress profile of each slice. The simulator determines a carrier mobility-based current for each slice, based on each slice carrier mobility. The simulator determines a carrier mobility for the MOS gate based on the carrier mobility-based current for each slice. The simulator determines an effective length for the MOS gate based on the length-based current.

    摘要翻译： 公开了一种用于确定金属氧化物半导体（MOS）门功能限制的计算机实现方法和计算机程序产品。 模拟器获得MOS门的多个片，每个片包括至少一个参数，该参数包括片栅宽度和片栅长度。 模拟器基于切片的切片门限长度确定每个切片的电流，以形成每个切片的基于长度的电流。 模拟器通过对每个切片的基于长度的电流求和来确定MOS栅极的基于长度的电流。 模拟器计算每个切片的应力分布。 模拟器基于每个切片的应力分布来确定每个切片的切片载波移动性。 模拟器基于每个切片载波移动性确定每个切片的基于载波移动性的电流。 模拟器基于每个切片的基于载波移动性的电流来确定MOS栅极的载流子迁移率。 模拟器基于长度电流确定MOS栅极的有效长度。

    Effective gate length circuit modeling based on concurrent length and mobility analysis
    2.
    发明授权
    Effective gate length circuit modeling based on concurrent length and mobility analysis 有权
    基于并发长度和移动性分析的有效栅长电路建模

    公开(公告)号：US08151240B2

    公开(公告)日：2012-04-03

    申请号：US12416222

    申请日：2009-04-01

    申请人： Kanak B. Agarwal ,  Vivek Joshi

    发明人： Kanak B. Agarwal ,  Vivek Joshi

    IPC分类号： G06F9/455 ,  G06F17/50 ,  G06F11/22

    CPC分类号： G06F17/5036

    摘要： Disclosed is a computer implemented method and computer program product to determine metal oxide semiconductor (MOS) gate functional limitations. A simulator obtains a plurality of slices of a MOS gate, the slices each comprising at least one parameter, the parameter comprising a slice gate width and a slice gate length. The simulator determines a current for each slice based on a slice gate length of the slice to form a length-based current for each slice. The simulator determines a length-based current for the MOS gate by summing the length-based current for each slice. The simulator calculates a stress profile for each slice. The simulator determines a slice carrier mobility for each slice based on the stress profile of each slice. The simulator determines a carrier mobility-based current for each slice, based on each slice carrier mobility. The simulator determines a carrier mobility for the MOS gate based on the carrier mobility-based current for each slice. The simulator determines an effective length for the MOS gate based on the length-based current.

    摘要翻译： 公开了一种用于确定金属氧化物半导体（MOS）门功能限制的计算机实现方法和计算机程序产品。 模拟器获得MOS门的多个片，每个片包括至少一个参数，该参数包括片栅宽度和片栅长度。 模拟器基于切片的切片门限长度确定每个切片的电流，以形成每个切片的基于长度的电流。 模拟器通过对每个切片的基于长度的电流求和来确定MOS栅极的基于长度的电流。 模拟器计算每个切片的应力分布。 模拟器基于每个切片的应力分布来确定每个切片的切片载波移动性。 模拟器基于每个切片载波移动性确定每个切片的基于载波移动性的电流。 模拟器基于每个切片的基于载波移动性的电流来确定MOS栅极的载流子迁移率。 模拟器基于长度电流确定MOS栅极的有效长度。

    Effective Gate Length Circuit Modeling Based On Concurrent Length And Mobility Analysis
    3.
    发明申请
    Effective Gate Length Circuit Modeling Based On Concurrent Length And Mobility Analysis 有权
    基于并行长度和移动性分析的有效栅长电路建模

    公开(公告)号：US20110283251A1

    公开(公告)日：2011-11-17

    申请号：US13187201

    申请日：2011-07-20

    申请人： KANAK B. AGARWAL ,  Vivek Joshi

    发明人： KANAK B. AGARWAL ,  Vivek Joshi

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036

    摘要： Disclosed is a computer implemented method and computer program product to determine metal oxide semiconductor (MOS) gate functional limitations. A simulator obtains a plurality of slices of a MOS gate, the slices each comprising at least one parameter, the parameter comprising a slice gate width and a slice gate length. The simulator determines a current for each slice based on a slice gate length of the slice to form a length-based current for each slice. The simulator determines a length-based current for the MOS gate by summing the length-based current for each slice. The simulator calculates a stress profile for each slice. The simulator determines a slice carrier mobility for each slice based on the stress profile of each slice. The simulator determines a carrier mobility-based current for each slice, based on each slice carrier mobility. The simulator determines a carrier mobility for the MOS gate based on the carrier mobility-based current for each slice. The simulator determines an effective length for the MOS gate based on the length-based current.

    摘要翻译： 公开了一种用于确定金属氧化物半导体（MOS）门功能限制的计算机实现方法和计算机程序产品。 模拟器获得MOS门的多个片，每个片包括至少一个参数，该参数包括片栅宽度和片栅长度。 模拟器基于切片的切片门限长度确定每个切片的电流，以形成每个切片的基于长度的电流。 模拟器通过对每个切片的基于长度的电流求和来确定MOS栅极的基于长度的电流。 模拟器计算每个切片的应力分布。 模拟器基于每个切片的应力分布来确定每个切片的切片载波移动性。 模拟器基于每个切片载波移动性确定每个切片的基于载波移动性的电流。 模拟器基于每个切片的基于载波移动性的电流来确定MOS栅极的载流子迁移率。 模拟器基于长度电流确定MOS栅极的有效长度。

    Effective gate length circuit modeling based on concurrent length and mobility analysis
    4.
    发明授权
    Effective gate length circuit modeling based on concurrent length and mobility analysis 有权

    公开(公告)号：US08136079B2

    公开(公告)日：2012-03-13

    申请号：US13187201

    申请日：2011-07-20

    申请人： Kanak B. Agarwal ,  Vivek Joshi

    发明人： Kanak B. Agarwal ,  Vivek Joshi

    IPC分类号： G06F9/455 ,  G06F17/50 ,  G06F11/22

    CPC分类号： G06F17/5036

    摘要： Disclosed is a computer implemented method and computer program product to determine metal oxide semiconductor (MOS) gate functional limitations. A simulator obtains a plurality of slices of a MOS gate, the slices each comprising at least one parameter, the parameter comprising a slice gate width and a slice gate length. The simulator determines a current for each slice based on a slice gate length of the slice to form a length-based current for each slice. The simulator determines a length-based current for the MOS gate by summing the length-based current for each slice. The simulator calculates a stress profile for each slice. The simulator determines a slice carrier mobility for each slice based on the stress profile of each slice. The simulator determines a carrier mobility-based current for each slice, based on each slice carrier mobility. The simulator determines a carrier mobility for the MOS gate based on the carrier mobility-based current for each slice. The simulator determines an effective length for the MOS gate based on the length-based current.

    Data driven keeper for a domino circuit
    6.
    发明授权
    Data driven keeper for a domino circuit 有权
    数据驱动的守护者为多米诺骨牌电路

    公开(公告)号：US06559680B2

    公开(公告)日：2003-05-06

    申请号：US09448250

    申请日：1999-11-24

    申请人： Bharat Bhushan ,  Vivek Joshi

    发明人： Bharat Bhushan ,  Vivek Joshi

    IPC分类号： H03K19096

    CPC分类号： H03K19/0963

    摘要： A domino circuit may be provided with additional keeper transistors that are selectively activated when one of the input transistors in a logic structure has a low or inactive signal applied to it during the evaluation stage. Thus, the potential of the output node of the domino circuit may be maintained, improving the soft error rate.

    摘要翻译： 多米诺骨牌电路可以设置有附加的保持器晶体管，当逻辑结构中的一个输入晶体管在评估阶段期间施加到其上时，其被选择性地被激活。 因此，可以维持多米诺骨电路的输出节点的电位，提高软错误率。

    Method to reduce the power consumption of large PLAs by clock gating guided by recursive shannon decomposition of the and-plane
    8.
    发明授权
    Method to reduce the power consumption of large PLAs by clock gating guided by recursive shannon decomposition of the and-plane 失效
    通过由平面的递归香农分解引导的时钟门控来降低大型PLA的功耗的方法

    公开(公告)号：US07065732B1

    公开(公告)日：2006-06-20

    申请号：US09678175

    申请日：2000-09-28

    申请人： Victor Konrad ,  Vivek Joshi

    发明人： Victor Konrad ,  Vivek Joshi

    IPC分类号： G06F17/50 ,  H03K17/693 ,  H03K19/177

    CPC分类号： G06F17/5054

    摘要： A method that includes steps for determining an optimum splitting variable and dividing a programmable logic array (PLA) into a first sub-PLA and a second sub-PLA based on the splitting variable is presented. The method also provides for gating logic to be applied to the first sub-PLA and the second sub-PLA. Power consumption is then controlled in the first sub-PLA and the second sub-PLA so only one of the first sub-PLA and the second sub-PLA contributes to power consumption. In another embodiment, a PLA be recursively divided into a plurality of sub-PLAs.

    摘要翻译： 提出了一种方法，其包括用于确定最佳分割变量并基于分割变量将可编程逻辑阵列（PLA）划分为第一子PLA和第二子PLA的步骤。 该方法还提供了门控逻辑应用于第一辅助解决方案和第二辅助解决方案。 然后在第一sub-PLA和第二sub-PLA中控制功率消耗，所以第一sub-PLA和第二sub-PLA中只有一个有助于功耗。 在另一实施例中，PLA被递归地分成多个子PLA。

    Method and apparatus for low power domino decoding
    10.
    发明授权
    Method and apparatus for low power domino decoding 有权
    低功耗多米诺解码的方法和装置

    公开(公告)号：US06593776B2

    公开(公告)日：2003-07-15

    申请号：US09922434

    申请日：2001-08-03

    申请人： Sudarshan Kumar ,  Gaurav Mehta ,  Vivek Joshi

    发明人： Sudarshan Kumar ,  Gaurav Mehta ,  Vivek Joshi

    IPC分类号： H03K1994

    CPC分类号： G11C8/10

    摘要： A decoder includes multiple decode gates, each to provide one bit of a decoded output signal. At least two of the decode gates share a transistor. According to one aspect, each of the multiple decode gates is a skewed gate.

    摘要翻译： 解码器包括多个解码门，每个解码门提供解码输出信号的一位。 至少两个解码门共享晶体管。 根据一个方面，多个解码门中的每一个是偏斜门。