发明授权
- 专利标题: Effective gate length circuit modeling based on concurrent length and mobility analysis
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申请号: US13187201申请日: 2011-07-20
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公开(公告)号: US08136079B2公开(公告)日: 2012-03-13
- 发明人: Kanak B. Agarwal , Vivek Joshi
- 申请人: Kanak B. Agarwal , Vivek Joshi
- 申请人地址: US NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: US NY Armonk
- 代理机构: Garg Law Firm, PLLC
- 代理商 Rakesh Garg; Libby Z. Toub
- 主分类号: G06F9/455
- IPC分类号: G06F9/455 ; G06F17/50 ; G06F11/22
摘要:
Disclosed is a computer implemented method and computer program product to determine metal oxide semiconductor (MOS) gate functional limitations. A simulator obtains a plurality of slices of a MOS gate, the slices each comprising at least one parameter, the parameter comprising a slice gate width and a slice gate length. The simulator determines a current for each slice based on a slice gate length of the slice to form a length-based current for each slice. The simulator determines a length-based current for the MOS gate by summing the length-based current for each slice. The simulator calculates a stress profile for each slice. The simulator determines a slice carrier mobility for each slice based on the stress profile of each slice. The simulator determines a carrier mobility-based current for each slice, based on each slice carrier mobility. The simulator determines a carrier mobility for the MOS gate based on the carrier mobility-based current for each slice. The simulator determines an effective length for the MOS gate based on the length-based current.
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