发明授权
US08143646B2 Stacking fault and twin blocking barrier for integrating III-V on Si
有权
堆叠故障和双阻挡屏障，用于在Si上集成III-V
- 专利标题： Stacking fault and twin blocking barrier for integrating III-V on Si
- 专利标题（中）： 堆叠故障和双阻挡屏障，用于在Si上集成III-V
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申请号： US11498901申请日： 2006-08-02
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公开(公告)号： US08143646B2公开(公告)日： 2012-03-27
- 发明人: Mantu K. Hudait , Mohamad A. Shaheen , Loren A. Chow , Peter G. Tolchinsky , Joel M. Fastenau , Dmitri Loubychev , Amy W. K. Liu
- 申请人： Mantu K. Hudait , Mohamad A. Shaheen , Loren A. Chow , Peter G. Tolchinsky , Joel M. Fastenau , Dmitri Loubychev , Amy W. K. Liu
- 申请人地址： US CA Santa Clara
- 专利权人： Intel Corporation
- 当前专利权人： Intel Corporation
- 当前专利权人地址： US CA Santa Clara
- 代理机构： Blakely, Sokoloff, Taylor & Zafman LLP
- 主分类号： H01L21/02
- IPC分类号： H01L21/02
摘要：
A stacking fault and twin blocking barrier for forming a III-V device layer on a silicon substrate and the method of manufacture is described. Embodiments of the present invention enable III-V InSb device layers with defect densities below 1×108 cm−2 to be formed on silicon substrates. In an embodiment of the present invention, a buffer layer is positioned between a III-V device layer and a silicon substrate to glide dislocations. In an embodiment of the present invention, GaSb buffer layer is selected on the basis of lattice constant, band gap, and melting point to prevent many lattice defects from propagating out of the buffer into the III-V device layer. In a specific embodiment, a III-V InSb device layer is formed directly on the GaSb buffer.
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