The 1T floating-body DRAM cell device includes a floating body for storing information of the DRAM cell device, a source and a drain formed on respective sides of the floating body, a gate insulating layer formed on a top of the floating body, a gate electrode formed on a top of the gate insulating layer, a gate stack formed under the floating body and configured to have a charge storage node for storing electric charges, and a control electrode formed on a lower side of the gate stack or partially or completely surrounded by the gate stack. The DRAM cell device performs “write0” and “write1” operations or a read operation. The DRAM cell device performs a non-volatile program operation or a non-volatile erase operation.