A power-mode-aware (PMA) clock tree and a synthesis method thereof are provided. The clock tree includes a sub clock tree and a PMA buffer. The sub clock tree transmits a delayed clock signal to a function module, wherein a power mode of the function module is determined according to a power information. The PMA buffer is coupled to the sub clock tree. The PMA buffer determines the delay time of a system clock signal according to the power information delays the system clock signal, and outputs the delayed system clock signal to the sub clock tree as the delayed clock signal.