发明授权
US08194461B2 Semiconductor memory device having dummy cells in NAND strings applied with an additional program voltage after erasure and prior to data programming
有权
半导体存储器件在NAND串中具有虚拟单元，在擦除之后并在数据编程之前施加额外的编程电压
- 专利标题： Semiconductor memory device having dummy cells in NAND strings applied with an additional program voltage after erasure and prior to data programming
- 专利标题（中）： 半导体存储器件在NAND串中具有虚拟单元，在擦除之后并在数据编程之前施加额外的编程电压
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申请号： US12985427申请日： 2011-01-06
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公开(公告)号： US08194461B2公开(公告)日： 2012-06-05
- 发明人: Yasukazu Kosaki , Noboru Shibata
- 申请人： Yasukazu Kosaki , Noboru Shibata
- 申请人地址： JP Tokyo
- 专利权人： Kabushiki Kaisha Toshiba
- 当前专利权人： Kabushiki Kaisha Toshiba
- 当前专利权人地址： JP Tokyo
- 代理机构： Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- 优先权： JP2006-264935 20060928
- 主分类号： G11C16/10
- IPC分类号： G11C16/10
摘要：
A semiconductor memory device with NAND cell units arranged therein, the NAND cell unit including: a plurality of electrically rewritable and non-volatile memory cells connected in series; first and second select gate transistors disposed at the both ends of the NAND cell unit for coupling it to a bit line and a source line, respectively; and dummy cells disposed adjacent to the first and second select gate transistors in the NAND cell unit, wherein the dummy cells are set at a state with a threshold voltage higher than that of an erase state of the memory cell.
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