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    Semiconductor memory device having dummy cells in NAND strings applied with an additional program voltage after erasure and prior to data programming
    1.
    发明授权
    Semiconductor memory device having dummy cells in NAND strings applied with an additional program voltage after erasure and prior to data programming 有权
    半导体存储器件在NAND串中具有虚拟单元，在擦除之后并在数据编程之前施加额外的编程电压

    公开(公告)号：US08194461B2

    公开(公告)日：2012-06-05

    申请号：US12985427

    申请日：2011-01-06

    申请人： Yasukazu Kosaki ,  Noboru Shibata

    发明人： Yasukazu Kosaki ,  Noboru Shibata

    IPC分类号： G11C16/10

    CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/3454 ,  G11C2211/5621 ,  G11C2211/5634

    摘要： A semiconductor memory device with NAND cell units arranged therein, the NAND cell unit including: a plurality of electrically rewritable and non-volatile memory cells connected in series; first and second select gate transistors disposed at the both ends of the NAND cell unit for coupling it to a bit line and a source line, respectively; and dummy cells disposed adjacent to the first and second select gate transistors in the NAND cell unit, wherein the dummy cells are set at a state with a threshold voltage higher than that of an erase state of the memory cell.

    摘要翻译： 一种其中布置有NAND单元单元的半导体存储器件，所述NAND单元单元包括：串联连接的多个电可重写和非易失性存储单元; 设置在NAND单元单元的两端的第一和第二选择栅晶体管分别用于将其耦合到位线和源极线; 以及在NAND单元单元中与第一和第二选择栅极晶体管相邻设置的虚设单元，其中虚设单元被设置为具有比存储单元的擦除状态的阈值电压高的阈值电压的状态。

    SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR CONTROLLING THE SAME
    2.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR CONTROLLING THE SAME 有权
    半导体存储器件及其控制方法

    公开(公告)号：US20080239822A1

    公开(公告)日：2008-10-02

    申请号：US11862539

    申请日：2007-09-27

    申请人： Yasukazu Kosaki ,  Noboru Shibata

    发明人： Yasukazu Kosaki ,  Noboru Shibata

    IPC分类号： G11C16/04 ,  G11C16/06

    CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/3454 ,  G11C2211/5621 ,  G11C2211/5634

    摘要： A semiconductor memory device with NAND cell units arranged therein, the NAND cell unit including: a plurality of electrically rewritable and non-volatile memory cells connected in series; first and second select gate transistors disposed at the both ends of the NAND cell unit for coupling it to a bit line and a source line, respectively; and dummy cells disposed adjacent to the first and second select gate transistors in the NAND cell unit, wherein the dummy cells are set at a state with a threshold voltage higher than that of an erase state of the memory cell.

    摘要翻译： 一种其中布置有NAND单元单元的半导体存储器件，所述NAND单元单元包括：串联连接的多个电可重写和非易失性存储单元; 设置在NAND单元单元的两端的第一和第二选择栅晶体管分别用于将其耦合到位线和源极线; 以及在NAND单元单元中与第一和第二选择栅极晶体管相邻设置的虚设单元，其中虚设单元被设置为具有比存储单元的擦除状态的阈值电压高的阈值电压的状态。

    SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR CONTROLLING THE SAME
    3.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR CONTROLLING THE SAME 有权
    半导体存储器件及其控制方法

    公开(公告)号：US20110096605A1

    公开(公告)日：2011-04-28

    申请号：US12985427

    申请日：2011-01-06

    申请人： Yasukazu Kosaki ,  Noboru Shibata

    发明人： Yasukazu Kosaki ,  Noboru Shibata

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/3454 ,  G11C2211/5621 ,  G11C2211/5634

    摘要： A semiconductor memory device with NAND cell units arranged therein, the NAND cell unit including: a plurality of electrically rewritable and non-volatile memory cells connected in series; first and second select gate transistors disposed at the both ends of the NAND cell unit for coupling it to a bit line and a source line, respectively; and dummy cells disposed adjacent to the first and second select gate transistors in the NAND cell unit, wherein the dummy cells are set at a state with a threshold voltage higher than that of an erase state of the memory cell.

    摘要翻译： 一种其中布置有NAND单元单元的半导体存储器件，所述NAND单元单元包括：串联连接的多个电可重写和非易失性存储单元; 设置在NAND单元单元的两端的第一和第二选择栅晶体管分别用于将其耦合到位线和源极线; 以及在NAND单元单元中与第一和第二选择栅极晶体管相邻设置的虚设单元，其中虚设单元被设置为具有比存储单元的擦除状态的阈值电压高的阈值电压的状态。

    Semiconductor memory device realizing a channel voltage control scheme adopting dummy cells with threshold voltage higher than threshold voltage of erased memory cells and method thereof
    4.
    发明授权
    Semiconductor memory device realizing a channel voltage control scheme adopting dummy cells with threshold voltage higher than threshold voltage of erased memory cells and method thereof 有权
    实现采用阈值电压高于擦除存储单元的阈值电压的虚拟单元的信道电压控制方案及其方法

    公开(公告)号：US07869280B2

    公开(公告)日：2011-01-11

    申请号：US11862539

    申请日：2007-09-27

    申请人： Yasukazu Kosaki ,  Noboru Shibata

    发明人： Yasukazu Kosaki ,  Noboru Shibata

    IPC分类号： G11C16/10

    CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/3454 ,  G11C2211/5621 ,  G11C2211/5634

    摘要： A semiconductor memory device with NAND cell units arranged therein, the NAND cell unit including: a plurality of electrically rewritable and non-volatile memory cells connected in series; first and second select gate transistors disposed at the both ends of the NAND cell unit for coupling it to a bit line and a source line, respectively; and dummy cells disposed adjacent to the first and second select gate transistors in the NAND cell unit, wherein the dummy cells are set at a state with a threshold voltage higher than that of an erase state of the memory cell.

    摘要翻译： 一种其中布置有NAND单元单元的半导体存储器件，所述NAND单元单元包括：串联连接的多个电可重写和非易失性存储单元; 设置在NAND单元单元的两端的第一和第二选择栅晶体管分别用于将其耦合到位线和源极线; 以及在NAND单元单元中与第一和第二选择栅极晶体管相邻设置的虚设单元，其中虚设单元被设置为具有比存储单元的擦除状态的阈值电压高的阈值电压的状态。