发明授权
- 专利标题: Protocol for maintaining cache coherency in a CMP
- 专利标题(中): 用于在CMP中维护高速缓存一致性的协议
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申请号: US10749752申请日: 2003-12-30
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公开(公告)号: US08209490B2公开(公告)日: 2012-06-26
- 发明人: Matthew Mattina , George Z. Chrysos
- 申请人: Matthew Mattina , George Z. Chrysos
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 代理机构: Mnemoglyphics, LLC
- 代理商 Lawrence M. Mennemeier
- 主分类号: G06F12/00
- IPC分类号: G06F12/00 ; G06F13/00 ; G06F13/28 ; G06F9/26 ; G06F9/34
摘要:
The present application is a protocol for maintaining cache coherency in a CMP. The CMP design contains multiple processor cores with each core having it own private cache. In addition, the CMP has a single on-ship shared cache. The processor cores and the shared cache may be connected together with a synchronous, unbuffered bidirectional ring interconnect. In the present protocol, a single INVALIDATEANDACKNOWLEDGE message is sent on the ring to invalidate a particular core and acknowledge a particular core.
公开/授权文献
- US20050144390A1 Protocol for maintaining cache coherency in a CMP 公开/授权日:2005-06-30