发明授权
US08217428B2 Integrated circuit including gate electrode level region including at least three linear-shaped conductive structures of equal length having aligned ends and positioned at equal pitch and forming multiple gate electrodes of transistors of different type
有权
集成电路，包括栅极电平区域，其包括至少三个相等长度的线性导电结构，其具有对准的端部并以相等间距定位，并形成不同类型的晶体管的多个栅电极
- 专利标题： Integrated circuit including gate electrode level region including at least three linear-shaped conductive structures of equal length having aligned ends and positioned at equal pitch and forming multiple gate electrodes of transistors of different type
- 专利标题（中）： 集成电路，包括栅极电平区域，其包括至少三个相等长度的线性导电结构，其具有对准的端部并以相等间距定位，并形成不同类型的晶体管的多个栅电极
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申请号： US12571351申请日： 2009-09-30
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公开(公告)号： US08217428B2公开(公告)日： 2012-07-10
- 发明人: Scott T. Becker , Michael C. Smayling
- 申请人： Scott T. Becker , Michael C. Smayling
- 申请人地址： US CA Los Gatos
- 专利权人： Tela Innovations, Inc.
- 当前专利权人： Tela Innovations, Inc.
- 当前专利权人地址： US CA Los Gatos
- 代理机构： Martine Penilla Group, LLP
- 主分类号： H01L27/10
- IPC分类号： H01L27/10
摘要：
A cell of a semiconductor device is disclosed to include a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell also includes a gate electrode level including a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level is fabricated from a respective originating rectangular-shaped layout feature. The gate electrode level includes conductive features defined along at least four different virtual lines of extent in the first parallel direction. A width of the conductive features within the gate electrode level is measured perpendicular to the first parallel direction and is less than a wavelength of light used in a photolithography process to fabricate the conductive features. The cell also includes a number of interconnect levels formed above the gate electrode level.
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