Invention Grant
US08229020B2 Integrated equalization and CDR adaptation engine with single error monitor circuit
有权
具有单错误监控电路的集成均衡和CDR适配引擎
- Patent Title: Integrated equalization and CDR adaptation engine with single error monitor circuit
- Patent Title (中): 具有单错误监控电路的集成均衡和CDR适配引擎
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Application No.: US12409236Application Date: 2009-03-23
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Publication No.: US08229020B2Publication Date: 2012-07-24
- Inventor: Dawei Huang , Muthukumar Vairavan , Dong Joon Yoon , Drew G. Doblar
- Applicant: Dawei Huang , Muthukumar Vairavan , Dong Joon Yoon , Drew G. Doblar
- Applicant Address: US CA Redwood City
- Assignee: Oracle America, Inc.
- Current Assignee: Oracle America, Inc.
- Current Assignee Address: US CA Redwood City
- Agency: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.
- Agent Rory D. Rankin
- Main IPC: H04B15/00
- IPC: H04B15/00 ; H04B1/10 ; H03K5/159

Abstract:
A data communications system and methods are disclosed. The system includes a transmitter for conveying a data signal filtered by a finite impulse response (FIR) filter to a receiver via a channel. The receiver equalizes the received data signal using a decision feedback equalizer (DFE) and the FIR. The receiver samples the data signal to determine an error signal and uses the error signal to adapt settings of a pre-cursor tap coefficient of the FIR, one or more post-cursor tap coefficients of the FIR, a phase of the recovered clock, and a coefficient of the DFE. To adapt the settings, the receiver determines the error signal based on an error sample taken from the data signal in a single clock cycle. To determine an error signal, the receiver samples the data signal at a phase estimated to correspond to a peak amplitude of a pulse response of the channel.
Public/Granted literature
- US20100238993A1 AN INTEGRATED EQUALIZATION AND CDR ADAPTATION ENGINE WITH SINGLE ERROR MONITOR CIRCUIT Public/Granted day:2010-09-23
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