公开(公告)号：US08243866B2

公开(公告)日：2012-08-14

申请号：US12116329

申请日：2008-05-07

申请人： Dawei Huang ,  Zuxu Qin ,  Drew G. Doblar ,  Waseem Ahmad ,  Dong Joon Yoon ,  Osman Javed

发明人： Dawei Huang ,  Zuxu Qin ,  Drew G. Doblar ,  Waseem Ahmad ,  Dong Joon Yoon ,  Osman Javed

IPC分类号： H04L7/00 ,  H04L27/06

CPC分类号： H04L7/0062

摘要： An analog baud rate clock and data recovery apparatus includes a first track and hold circuit that delays a received signal by one unit interval to create an odd signal; a second track and hold circuit that delays the received signal by one unit interval to create an even signal; a first comparator circuit; and a second comparator circuit. The first track and hold circuit outputs the odd signal to the first comparator circuit and the second comparator circuit. The second track and hold circuit outputs the even signal to the first comparator circuit and the second comparator circuit. The first comparator adds the odd signal to the even signal and outputs a first potential timing error. The second comparator subtracts the odd signal and the even signal and outputs a second potential timing error signal. A desired timing error signal is derived from the first and second potential timing error signals. The desired timing error signal is used to determine whether signal sampling is early or late.

摘要翻译： 模拟波特率时钟和数据恢复装置包括第一跟踪和保持电路，其将接收到的信号延迟一个单位间隔以产生奇数信号; 第二轨道和保持电路，其将接收到的信号延迟一个单位间隔以产生均匀信号; 第一比较器电路; 和第二比较器电路。 第一跟踪和保持电路将奇数信号输出到第一比较器电路和第二比较器电路。 第二跟踪和保持电路将偶信号输出到第一比较器电路和第二比较器电路。 第一个比较器将奇数信号加到偶数信号，并输出第一个电位定时误差。 第二比较器减去奇数信号和偶数信号，并输出第二电位定时误差信号。 从第一和第二电位定时误差信号导出期望的定时误差信号。 所需的定时误差信号用于确定信号采样是早还是晚。

公开(公告)号：US08229020B2

公开(公告)日：2012-07-24

申请号：US12409236

申请日：2009-03-23

申请人： Dawei Huang ,  Muthukumar Vairavan ,  Dong Joon Yoon ,  Drew G. Doblar

发明人： Dawei Huang ,  Muthukumar Vairavan ,  Dong Joon Yoon ,  Drew G. Doblar

IPC分类号： H04B15/00 ,  H04B1/10 ,  H03K5/159

CPC分类号： H04L25/03057 ,  H04L7/0337 ,  H04L2025/03503

摘要： A data communications system and methods are disclosed. The system includes a transmitter for conveying a data signal filtered by a finite impulse response (FIR) filter to a receiver via a channel. The receiver equalizes the received data signal using a decision feedback equalizer (DFE) and the FIR. The receiver samples the data signal to determine an error signal and uses the error signal to adapt settings of a pre-cursor tap coefficient of the FIR, one or more post-cursor tap coefficients of the FIR, a phase of the recovered clock, and a coefficient of the DFE. To adapt the settings, the receiver determines the error signal based on an error sample taken from the data signal in a single clock cycle. To determine an error signal, the receiver samples the data signal at a phase estimated to correspond to a peak amplitude of a pulse response of the channel.

摘要翻译： 公开了一种数据通信系统和方法。 该系统包括一个发射器，用于通过一个通道将一个由有限脉冲响应（FIR）滤波器滤波的数据信号传送到一个接收器。 接收机使用判决反馈均衡器（DFE）和FIR来均衡接收到的数据信号。 接收机采样数据信号以确定误差信号，并使用误差信号来适应FIR的前置光标抽头系数，FIR的一个或多个后置标签抽头系数，恢复时钟的相位的设置，以及 DFE的系数。 为了适应设置，接收机根据在单个时钟周期内从数据信号中获取的错误样本来确定误差信号。 为了确定误差信号，接收机以被估计为对应于信道的脉冲响应的峰值幅度的相位对数据信号进行采样。

公开(公告)号：US07107475B1

公开(公告)日：2006-09-12

申请号：US10690302

申请日：2003-10-21

申请人： Brian Amick ,  Dong Joon Yoon ,  Tri Tran ,  Gajendra Singh ,  Aparna Ramachandran ,  Claude Gauthier

发明人： Brian Amick ,  Dong Joon Yoon ,  Tri Tran ,  Gajendra Singh ,  Aparna Ramachandran ,  Claude Gauthier

IPC分类号： G06F1/12

CPC分类号： G06F1/12 ,  H03K2005/00241 ,  H03L7/0805 ,  H03L7/0814 ,  H03L7/091 ,  H03L7/10

摘要： A digital delay locked loop uses a delay array to delay an input signal by an amount indicated by a delay code. A phase of the resulting delayed signal is compared to a corresponding phase of the input signal, and dependent on the comparison, the delay code is updated to indicate whether the delay array needs to provide more delay or less delay. The digital delay locked loop also uses a detection circuit that monitors for a predetermined condition of the delay code. In response to detection of the predetermined condition, the delay code is automatically reset to a value different than a value of the delay code present at a previous reset or initial startup of the digital delay locked loop.

摘要翻译： 数字延迟锁定环使用延迟阵列将输入信号延迟由延迟码指示的量。 将所得到的延迟信号的相位与输入信号的相应相位进行比较，并且根据比较，更新延迟码以指示延迟阵列是否需要提供更多的延迟或更小的延迟。 数字延迟锁定环路还使用监视延迟码的预定条件的检测电路。 响应于预定条件的检测，延迟码被自动复位到与数字延迟锁定环的先前复位或初始启动时存在的延迟码的值不同的值。

公开(公告)号：US20090224806A1

公开(公告)日：2009-09-10

申请号：US12116329

申请日：2008-05-07

申请人： Dawei Huang ,  Zuxu Qin ,  Drew G. Doblar ,  Waseem Ahmad ,  Dong Joon Yoon ,  Osman Javed

发明人： Dawei Huang ,  Zuxu Qin ,  Drew G. Doblar ,  Waseem Ahmad ,  Dong Joon Yoon ,  Osman Javed

IPC分类号： H03K5/153

CPC分类号： H04L7/0062

摘要： An analog baud rate clock and data recovery apparatus includes a first track and hold circuit that delays a received signal by one unit interval to create an odd signal; a second track and hold circuit that delays the received signal by one unit interval to create an even signal; a first comparator circuit; and a second comparator circuit. The first track and hold circuit outputs the odd signal to the first comparator circuit and the second comparator circuit. The second track and hold circuit outputs the even signal to the first comparator circuit and the second comparator circuit. The first comparator adds the odd signal to the even signal and outputs a first potential timing error. The second comparator subtracts the odd signal and the even signal and outputs a second potential timing error signal. A desired timing error signal is derived from the first and second potential timing error signals. The desired timing error signal is used to determine whether signal sampling is early or late.

摘要翻译： 模拟波特率时钟和数据恢复装置包括第一跟踪和保持电路，其将接收到的信号延迟一个单位间隔以产生奇数信号; 第二轨道和保持电路，其将接收到的信号延迟一个单位间隔以产生均匀信号; 第一比较器电路; 和第二比较器电路。 第一跟踪和保持电路将奇数信号输出到第一比较器电路和第二比较器电路。 第二跟踪和保持电路将偶信号输出到第一比较器电路和第二比较器电路。 第一个比较器将奇数信号加到偶数信号，并输出第一个电位定时误差。 第二比较器减去奇数信号和偶数信号，并输出第二电位定时误差信号。 从第一和第二电位定时误差信号导出期望的定时误差信号。 所需的定时误差信号用于确定信号采样是早还是晚。

公开(公告)号：US20100238993A1

公开(公告)日：2010-09-23

申请号：US12409236

申请日：2009-03-23

申请人： Dawei Huang ,  Muthukumar Vairavan ,  Dong Joon Yoon ,  Drew G. Doblar

发明人： Dawei Huang ,  Muthukumar Vairavan ,  Dong Joon Yoon ,  Drew G. Doblar

IPC分类号： H04L27/01

CPC分类号： H04L25/03057 ,  H04L7/0337 ,  H04L2025/03503

摘要： A data communications system and methods are disclosed. The system includes a transmitter for conveying a data signal filtered by a finite impulse response (FIR) filter to a receiver via a channel. The receiver equalizes the received data signal using a decision feedback equalizer (DFE) and the FIR. The receiver samples the data signal to determine an error signal and uses the error signal to adapt settings of a pre-cursor tap coefficient of the FIR, one or more post-cursor tap coefficients of the FIR, a phase of the recovered clock, and a coefficient of the DFE. To adapt the settings, the receiver determines the error signal based on an error sample taken from the data signal in a single clock cycle. To determine an error signal, the receiver samples the data signal at a phase estimated to correspond to a peak amplitude of a pulse response of the channel.

摘要翻译： 公开了一种数据通信系统和方法。 该系统包括一个发射器，用于通过一个通道将一个由有限脉冲响应（FIR）滤波器滤波的数据信号传送到一个接收器。 接收机使用判决反馈均衡器（DFE）和FIR来均衡接收到的数据信号。 接收机采样数据信号以确定误差信号，并使用误差信号来适应FIR的前置光标抽头系数，FIR的一个或多个后置标签抽头系数，恢复时钟的相位的设置，以及 DFE的系数。 为了适应设置，接收机根据在单个时钟周期内从数据信号中获取的错误样本来确定误差信号。 为了确定误差信号，接收机以被估计为对应于信道的脉冲响应的峰值幅度的相位对数据信号进行采样。