Invention Grant
- Patent Title: Heat conduction for chip stacks and 3-D circuits
- Patent Title (中): 芯片堆叠和3-D电路的导热
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Application No.: US12773275Application Date: 2010-05-04
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Publication No.: US08232137B2Publication Date: 2012-07-31
- Inventor: Stephen Joseph Gaul , Francois Hebert
- Applicant: Stephen Joseph Gaul , Francois Hebert
- Applicant Address: US CA Milpitas
- Assignee: Intersil Americas Inc.
- Current Assignee: Intersil Americas Inc.
- Current Assignee Address: US CA Milpitas
- Agency: Fogg & Powers LLC
- Main IPC: H01L21/00
- IPC: H01L21/00

Abstract:
A semiconductor device assembly and method can include a single semiconductor layer or stacked semiconductor layers, for example semiconductor wafers or wafer sections (semiconductor dice). On each semiconductor layer, a diamond layer formed therethrough can aid in the routing and dissipation of heat. The diamond layer can include a first portion on the back of the semiconductor layer, and one or more second portions which extend vertically into the semiconductor layer, for example completely through the semiconductor layer. Thermal contact can then be made to the diamond layer to conduct heat away from the one or more semiconductor layers. A conductive via can be formed through the diamond layers to provide signal routing and heat dissipation capabilities.
Public/Granted literature
- US20110140126A1 HEAT CONDUCTION FOR CHIP STACKS AND 3-D CIRCUITS Public/Granted day:2011-06-16
Information query
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