公开(公告)号：US20120248627A1

公开(公告)日：2012-10-04

申请号：US13525523

申请日：2012-06-18

Applicant: Stephen Joseph Gaul ,  Francois Hebert

Inventor： Stephen Joseph Gaul ,  Francois Hebert

IPC: H01L23/48

CPC classification number: H01L23/3732 ,  H01L23/3677 ,  H01L23/481 ,  H01L24/05 ,  H01L24/06 ,  H01L24/14 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/06515 ,  H01L2224/1403 ,  H01L2224/14515 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/14 ,  H01L2924/00

Abstract: A semiconductor device assembly and method can include a single semiconductor layer or stacked semiconductor layers, for example semiconductor wafers or wafer sections (semiconductor dice). On each semiconductor layer, a diamond layer formed therethrough can aid in the routing and dissipation of heat. The diamond layer can include a first portion on the back of the semiconductor layer, and one or more second portions which extend vertically into the semiconductor layer, for example completely through the semiconductor layer. Thermal contact can then be made to the diamond layer to conduct heat away from the one or more semiconductor layers. A conductive via can be formed through the diamond layers to provide signal routing and heat dissipation capabilities.

Abstract translation: 半导体器件组件和方法可以包括单个半导体层或层叠的半导体层，例如半导体晶片或晶片部分（半导体晶片）。 在每个半导体层上，通过其形成的金刚石层可有助于散热和散热。 金刚石层可以包括半导体层背面的第一部分和垂直延伸到半导体层中的一个或多个第二部分，例如完全穿过半导体层。 然后可以对金刚石层进行热接触以将热量从一个或多个半导体层导出。 可以通过金刚石层形成导电通孔，以提供信号路由和散热能力。

公开(公告)号：US20110140126A1

公开(公告)日：2011-06-16

申请号：US12773275

申请日：2010-05-04

Applicant: Stephen Joseph Gaul ,  Francois Hebert

Inventor： Stephen Joseph Gaul ,  Francois Hebert

IPC: H01L23/373 ,  H01L21/768 ,  H01L23/48 ,  H01L21/02

CPC classification number: H01L23/3732 ,  H01L23/3677 ,  H01L23/481 ,  H01L24/05 ,  H01L24/06 ,  H01L24/14 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/06515 ,  H01L2224/1403 ,  H01L2224/14515 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/14 ,  H01L2924/00

Abstract: A semiconductor device assembly and method can include a single semiconductor layer or stacked semiconductor layers, for example semiconductor wafers or wafer sections (semiconductor dice). On each semiconductor layer, a diamond layer formed therethrough can aid in the routing and dissipation of heat. The diamond layer can include a first portion on the back of the semiconductor layer, and one or more second portions which extend vertically into the semiconductor layer, for example completely through the semiconductor layer. Thermal contact can then be made to the diamond layer to conduct heat away from the one or more semiconductor layers. A conductive via can be formed through the diamond layers to provide signal routing and heat dissipation capabilities.

Abstract translation: 半导体器件组件和方法可以包括单个半导体层或层叠的半导体层，例如半导体晶片或晶片部分（半导体晶片）。 在每个半导体层上，通过其形成的金刚石层可有助于散热和散热。 金刚石层可以包括半导体层背面的第一部分和垂直延伸到半导体层中的一个或多个第二部分，例如完全穿过半导体层。 然后可以对金刚石层进行热接触以将热量从一个或多个半导体层导出。 可以通过金刚石层形成导电通孔，以提供信号路由和散热能力。

公开(公告)号：US08232137B2

公开(公告)日：2012-07-31

申请号：US12773275

申请日：2010-05-04

Applicant: Stephen Joseph Gaul ,  Francois Hebert

Inventor： Stephen Joseph Gaul ,  Francois Hebert

IPC: H01L21/00

CPC classification number: H01L23/3732 ,  H01L23/3677 ,  H01L23/481 ,  H01L24/05 ,  H01L24/06 ,  H01L24/14 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/06515 ,  H01L2224/1403 ,  H01L2224/14515 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/14 ,  H01L2924/00

Abstract: A semiconductor device assembly and method can include a single semiconductor layer or stacked semiconductor layers, for example semiconductor wafers or wafer sections (semiconductor dice). On each semiconductor layer, a diamond layer formed therethrough can aid in the routing and dissipation of heat. The diamond layer can include a first portion on the back of the semiconductor layer, and one or more second portions which extend vertically into the semiconductor layer, for example completely through the semiconductor layer. Thermal contact can then be made to the diamond layer to conduct heat away from the one or more semiconductor layers. A conductive via can be formed through the diamond layers to provide signal routing and heat dissipation capabilities.

Abstract translation: 半导体器件组件和方法可以包括单个半导体层或层叠的半导体层，例如半导体晶片或晶片部分（半导体晶片）。 在每个半导体层上，通过其形成的金刚石层可有助于散热和散热。 金刚石层可以包括半导体层背面的第一部分和垂直延伸到半导体层中的一个或多个第二部分，例如完全穿过半导体层。 然后可以对金刚石层进行热接触以将热量从一个或多个半导体层导出。 可以通过金刚石层形成导电通孔，以提供信号路由和散热能力。

公开(公告)号：US20110115047A1

公开(公告)日：2011-05-19

申请号：US12794236

申请日：2010-06-04

Applicant: Francois Hebert ,  Aaron Gibby ,  Stephen Joseph Gaul

Inventor： Francois Hebert ,  Aaron Gibby ,  Stephen Joseph Gaul

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/331 ,  H01L29/73 ,  H01L21/306

CPC classification number: H01L21/743 ,  H01L21/76229 ,  H01L21/8222 ,  H01L21/8228 ,  H01L21/8249 ,  H01L27/0733 ,  H01L28/90 ,  H01L29/66272

Abstract: Methods and structures for a semiconductor device can use mask openings of varying widths to form structures of different depths, different materials, and different functionality. For example, processes and structures for forming shallow trench isolation, deep isolation, trench capacitors, base, emitter, and collector, among other structures for a lateral bipolar transistor are described.

Abstract translation: 半导体器件的方法和结构可以使用不同宽度的掩模开口来形成不同深度，不同材料和不同功能的结构。 例如，描述了用于形成浅沟槽隔离，深隔离，沟槽电容器，基极，发射极和集电极以及横向双极晶体管的其它结构的工艺和结构。

公开(公告)号：US09257525B2

公开(公告)日：2016-02-09

申请号：US13283139

申请日：2011-10-27

Applicant: I-Shan Sun ,  Rick Carlton Jerome ,  Francois Hebert

Inventor： I-Shan Sun ,  Rick Carlton Jerome ,  Francois Hebert

IPC: H01L21/00 ,  H01L29/66 ,  H01L23/48 ,  H01L23/535 ,  H01L21/74 ,  H01L27/06

CPC classification number: H01L29/66204 ,  H01L21/743 ,  H01L23/481 ,  H01L23/535 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for through active-silicon via integration is provided. The method comprises forming an electrical device in a handle wafer. The method also comprises forming an isolation layer over the handle wafer and the electrical device and joining an active layer to the isolation layer. Further, the method comprises forming at least one trench through the active layer and the isolation layer to expose a portion of the handle wafer and depositing an electrically conductive material in the at least one trench, the electrically conductive material providing an electrical connection to the electrical device through the active layer.

Abstract translation: 提供了一种通过积分硅通过集成的方法。 该方法包括在处理晶片中形成电气装置。 该方法还包括在手柄晶片和电气装置上形成隔离层，并将活性层连接到隔离层。 此外，该方法包括通过有源层和隔离层形成至少一个沟槽，以暴露处理晶片的一部分并在至少一个沟槽中沉积导电材料，导电材料提供与电 设备通过活动层。

公开(公告)号：US09209173B2

公开(公告)日：2015-12-08

申请号：US13415384

申请日：2012-03-08

Applicant: Francois Hebert

Inventor： Francois Hebert

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/417 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78 ,  H02M7/00

CPC classification number: H01L27/088 ,  H01L21/26513 ,  H01L21/823437 ,  H01L21/823487 ,  H01L23/535 ,  H01L23/62 ,  H01L29/0619 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/456 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/66696 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7802 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7816 ,  H01L29/7835 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/30107 ,  H01L2924/3025 ,  H02M7/003 ,  H01L2924/00

Abstract: A voltage converter includes an output circuit having a high-side device and a low-side device which can be formed on a single die (a “PowerDie”). The high-side device can include a lateral diffused metal oxide semiconductor (LDMOS) while the low-side device can include a trench-gate vertical diffused metal oxide semiconductor (VDMOS). The voltage converter can further include a controller circuit on a different die which can be electrically coupled to, and co-packaged with the output circuit.

Abstract translation: 电压转换器包括具有可以形成在单个管芯（“PowerDie”）上的高侧器件和低侧器件的输出电路。 高侧器件可以包括横向扩散金属氧化物半导体（LDMOS），而低侧器件可以包括沟槽栅极垂直扩散金属氧化物半导体（VDMOS）。 电压转换器还可以包括在不同管芯上的控制器电路，其可以电耦合到输出电路并与输出电路共同封装。

公开(公告)号：US20120098090A1

公开(公告)日：2012-04-26

申请号：US13069789

申请日：2011-03-23

Applicant: Francois Hebert ,  Shea Petricek ,  Nikhil Kelkar

Inventor： Francois Hebert ,  Shea Petricek ,  Nikhil Kelkar

IPC: H01L29/92 ,  H01L21/56

CPC classification number: H01L23/49589 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/16 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/16265 ,  H01L2224/371 ,  H01L2224/37147 ,  H01L2224/3718 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48265 ,  H01L2224/4912 ,  H01L2224/49175 ,  H01L2224/73207 ,  H01L2224/73221 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01042 ,  H01L2924/01056 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/19106 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A power converter device comprises a substrate, a power die mounted on the substrate, and a capacitor die mounted over the power die in a stacked configuration. The capacitor die is electrically coupled to the power die. A packaging material encapsulates the power die and the capacitor die. An integrated circuit die can also be mounted to the substrate and electrically coupled to the power die to receive power signals from the power die, with the packaging material also encapsulating the integrated circuit die.

Abstract translation: 功率转换器装置包括衬底，安装在衬底上的功率管芯和以堆叠构造安装在功率管芯上的电容器管芯。 电容器管芯电耦合到功率管芯。 封装材料封装了电源管芯和电容器管芯。 集成电路管芯也可以安装到衬底上并且电耦合到功率管芯以从功率管芯接收功率信号，封装材料也封装集成电路管芯。

公开(公告)号：US20120007097A1

公开(公告)日：2012-01-12

申请号：US12944163

申请日：2010-11-11

Applicant: Francois Hebert

Inventor： Francois Hebert

IPC: H01L29/20 ,  H01L29/872 ,  H01L21/329

CPC classification number: H01L29/872 ,  H01L29/0619 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/66143

Abstract: A Schottky diode comprising a merged guard ring and field plate defining a Schottky contact region is provided. A Schottky metal is formed over at least partially over the Schottky contact region and at least partially over the merged guard ring and field plate.

Abstract translation: 提供了包括合并的保护环和限定肖特基接触区域的场板的肖特基二极管。 肖特基金属至少部分地形成在肖特基接触区域上并且至少部分地在合并的保护环和场板上形成。

公开(公告)号：US20110107589A1

公开(公告)日：2011-05-12

申请号：US13007551

申请日：2011-01-14

Applicant: Francois Hebert ,  Tao Feng ,  Jun Lu

Inventor： Francois Hebert ,  Tao Feng ,  Jun Lu

IPC: H01F7/06

CPC classification number: H01F17/0033 ,  H01F1/344 ,  H01F41/046 ,  H01F2017/002 ,  Y10T29/4902

Abstract: An inductor may include a planar ferrite core. A first group of one or more grooves is formed in a first side of the ferrite core. A second group of two or more grooves is formed in a second side of the ferrite core. The grooves in the first and second groups are oriented such that each groove in the first group overlaps with two corresponding grooves in the second group. A first plurality of vias communicates through the ferrite core between the first and second sides of the ferrite core. Each via is located where a groove in the first group overlaps with a groove in the second group. A conductive material is disposed in the first and second groups of grooves and in the vias to form an inductor coil.

Abstract translation: 电感器可以包括平面铁氧体磁芯。 第一组一个或多个凹槽形成在铁氧体磁芯的第一侧。 在铁氧体磁芯的第二侧形成有第二组两个或多个凹槽。 第一组和第二组中的凹槽被定向成使得第一组中的每个凹槽与第二组中的两个相应的凹槽重叠。 第一多个通孔在铁氧体磁芯的第一和第二侧之间通过铁氧体磁芯连通。 每个通孔位于第一组中的凹槽与第二组中的凹槽重叠的位置。 导电材料设置在第一和第二组沟槽和通孔中以形成电感线圈。

公开(公告)号：US20090322461A1

公开(公告)日：2009-12-31

申请号：US12165423

申请日：2008-06-30

Applicant: Francois Hebert ,  Tao Feng ,  Jun Lu

Inventor： Francois Hebert ,  Tao Feng ,  Jun Lu

IPC: H01F27/02

CPC classification number: H01F17/0033 ,  H01F1/344 ,  H01F41/046 ,  H01F2017/002 ,  Y10T29/4902

Abstract: An inductor may include a planar ferrite core. A first group of one or more grooves is formed in a first side of the ferrite core. A second group of two or more grooves is formed in a second side of the ferrite core. The grooves in the first and second groups are oriented such that each groove in the first group overlaps with two corresponding grooves in the second group. A first plurality of vias communicates through the ferrite core between the first and second sides of the ferrite core. Each via is located where a groove in the first group overlaps with a groove in the second group. A conductive material is disposed in the first and second groups of grooves and in the vias to form an inductor coil.

Abstract translation: 电感器可以包括平面铁氧体磁芯。 第一组一个或多个凹槽形成在铁氧体磁芯的第一侧。 在铁氧体磁芯的第二侧形成有第二组两个或多个凹槽。 第一组和第二组中的凹槽被定向成使得第一组中的每个凹槽与第二组中的两个相应的凹槽重叠。 第一多个通孔在铁氧体磁芯的第一和第二侧之间通过铁氧体磁芯连通。 每个通孔位于第一组中的凹槽与第二组中的凹槽重叠的位置。 导电材料设置在第一和第二组沟槽和通孔中以形成电感线圈。