发明授权
- 专利标题： Packaging an integrated circuit die with backside metallization
- 专利标题（中）： 封装具有背面金属化的集成电路管芯
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申请号： US12184377申请日： 2008-08-01
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公开(公告)号： US08236609B2公开(公告)日： 2012-08-07
- 发明人: Lakshmi N. Ramanathan , Craig S. Amrine , Jianwen Xu
- 申请人： Lakshmi N. Ramanathan , Craig S. Amrine , Jianwen Xu
- 申请人地址： US TX Austin
- 专利权人： Freescale Semiconductor, Inc.
- 当前专利权人： Freescale Semiconductor, Inc.
- 当前专利权人地址： US TX Austin
- 代理机构： Meschkow & Gresham, P.L.C.
- 主分类号： H01L21/56
- IPC分类号： H01L21/56
摘要：
A method (32) of packaging integrated circuit (IC) dies (48) includes applying (36) a laminating material (44) to a wafer (40), and separating (46) the wafer (40) into multiple IC dies (48) such that the laminating material (44) is applied to back surfaces (52) of the IC dies (48). Each of the IC dies (48) is positioned (62) with an active surface (50) facing a support substrate (56). An encapsulant layer (72) is formed (64) overlying the laminating material (44) and the back surfaces (52) of the IC dies (48) from a molding compound (66). The molding compound (66) and the laminating material (44) are removed from the back surfaces (52) of the IC dies (48) to form (76) openings (78) exposing the back surfaces (52). Conductive material (84, 88) is placed in the openings (78) and functions as a heat sink and/or a ground for the IC dies (48).