公开(公告)号：US20110027984A1

公开(公告)日：2011-02-03

申请号：US12901854

申请日：2010-10-11

申请人： Lakshmi N. Ramanathan ,  Tien Yu T. Lee ,  Jinbang Tang

发明人： Lakshmi N. Ramanathan ,  Tien Yu T. Lee ,  Jinbang Tang

IPC分类号： H01L21/44

CPC分类号： H01L24/10 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05026 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05164 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2924/00014

摘要： An electronic device can include an interconnect level including a bonding pad region. An insulating layer can overlie the interconnect level and include an opening over the bonding pad region. In one embodiment, a conductive stud can lie within the opening and can be substantially encapsulated. In another embodiment, the electronic device can include a barrier layer lying along a side and a bottom of the opening and a conductive stud lying within the opening. The conductive stud can substantially fill the opening. A majority of the conductive stud can lie within the opening. In still another embodiment, a process for forming an electronic device can include forming a conductive stud within the opening wherein from a top view, the conductive stud lies substantially completely within the opening. The process can also include forming a second barrier layer overlying the conductive stud.

摘要翻译： 电子设备可以包括包括焊盘区域的互连级别。 绝缘层可以覆盖互连水平并且包括在焊盘区域上方的开口。 在一个实施例中，导电柱可以位于开口内并且可以基本上封装。 在另一个实施例中，电子设备可以包括位于开口的一侧和底部以及位于开口内的导电柱的阻挡层。 导电螺柱可以基本上填充开口。 导电螺柱的大部分可以位于开口内。 在另一个实施例中，用于形成电子设备的方法可以包括在开口内形成导电柱，其中从顶视图，导电柱基本上完全位于开口内。 该方法还可以包括形成覆盖导电柱的第二阻挡层。

公开(公告)号：US20160163623A1

公开(公告)日：2016-06-09

申请号：US15041742

申请日：2016-02-11

申请人： Lakshminarayan Viswanathan ,  Lakshmi N. Ramanathan ,  Audel A. Sanchez ,  Fernando A. Santos

发明人： Lakshminarayan Viswanathan ,  Lakshmi N. Ramanathan ,  Audel A. Sanchez ,  Fernando A. Santos

IPC分类号： H01L23/495 ,  H01L23/00 ,  H01L23/04 ,  H01L23/31

CPC分类号： H01L23/49568 ,  H01L21/4825 ,  H01L21/4882 ,  H01L21/561 ,  H01L21/568 ,  H01L23/04 ,  H01L23/3107 ,  H01L23/3677 ,  H01L23/49506 ,  H01L23/49531 ,  H01L23/49541 ,  H01L23/49575 ,  H01L23/49582 ,  H01L24/32 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A packaged semiconductor device may include a termination surface having terminations configured as leadless interconnects to be surface mounted to a printed circuit board. A first flange has a first surface and a second surface. The first surface provides a first one of the terminations, and the second surface is opposite to the first surface. A second flange also has a first surface and a second surface, with the first surface providing a second one of the terminations, and the second surface is opposite to the first surface. A die is mounted to the second surface of the first flange with a material having a melting point in excess of 240° C. An electrical interconnect extends between the die and the second surface of the second flange opposite the termination surface, such that the electrical interconnect, first flange and second flange are substantially housed within a body.

公开(公告)号：US08236609B2

公开(公告)日：2012-08-07

申请号：US12184377

申请日：2008-08-01

申请人： Lakshmi N. Ramanathan ,  Craig S. Amrine ,  Jianwen Xu

发明人： Lakshmi N. Ramanathan ,  Craig S. Amrine ,  Jianwen Xu

IPC分类号： H01L21/56

CPC分类号： H01L23/3114 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3135 ,  H01L23/4334 ,  H01L24/19 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/2518 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00

摘要： A method (32) of packaging integrated circuit (IC) dies (48) includes applying (36) a laminating material (44) to a wafer (40), and separating (46) the wafer (40) into multiple IC dies (48) such that the laminating material (44) is applied to back surfaces (52) of the IC dies (48). Each of the IC dies (48) is positioned (62) with an active surface (50) facing a support substrate (56). An encapsulant layer (72) is formed (64) overlying the laminating material (44) and the back surfaces (52) of the IC dies (48) from a molding compound (66). The molding compound (66) and the laminating material (44) are removed from the back surfaces (52) of the IC dies (48) to form (76) openings (78) exposing the back surfaces (52). Conductive material (84, 88) is placed in the openings (78) and functions as a heat sink and/or a ground for the IC dies (48).

摘要翻译： 封装集成电路（IC）模具（48）的方法（32）包括将层压材料（44）施加（36）到晶片（40），并将晶片（40）分离成多个IC模具（48） ），使得层压材料（44）被施加到IC管芯（48）的后表面（52）。 每个IC管芯（48）被定位（62），其中活动表面（50）面向支撑衬底（56）。 从模制化合物（66）形成覆盖层叠材料（44）和IC模具（48）的后表面（52）的密封剂层（64）（64）。 从IC模具（48）的背面（52）去除模塑料（66）和层压材料（44），以形成露出背面（52）的开口（78）。 导电材料（84,88）被放置在开口（78）中并且用作IC模具（48）的散热器和/或接地。

公开(公告)号：US20100029045A1

公开(公告)日：2010-02-04

申请号：US12184377

申请日：2008-08-01

申请人： Lakshmi N. Ramanathan ,  Craig S. Amrine ,  Jianwen Xu

发明人： Lakshmi N. Ramanathan ,  Craig S. Amrine ,  Jianwen Xu

IPC分类号： H01L21/56

CPC分类号： H01L23/3114 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3135 ,  H01L23/4334 ,  H01L24/19 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/2518 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00

摘要： A method (32) of packaging integrated circuit (IC) dies (48) includes applying (36) a laminating material (44) to a wafer (40), and separating (46) the wafer (40) into multiple IC dies (48) such that the laminating material (44) is applied to back surfaces (52) of the IC dies (48). Each of the IC dies (48) is positioned (62) with an active surface (50) facing a support substrate (56). An encapsulant layer (72) is formed (64) overlying the laminating material (44) and the back surfaces (52) of the IC dies (48) from a molding compound (66). The molding compound (66) and the laminating material (44) are removed from the back surfaces (52) of the IC dies (48) to form (76) openings (78) exposing the back surfaces (52). Conductive material (84, 88) is placed in the openings (78) and functions as a heat sink and/or a ground for the IC dies (48).

摘要翻译： 封装集成电路（IC）模具（48）的方法（32）包括将层压材料（44）施加（36）到晶片（40），并将晶片（40）分离成多个IC模具（48） ），使得层压材料（44）被施加到IC管芯（48）的后表面（52）。 每个IC管芯（48）被定位（62），其中活动表面（50）面向支撑衬底（56）。 从模制化合物（66）形成覆盖层叠材料（44）和IC模具（48）的后表面（52）的密封剂层（64）（64）。 从IC模具（48）的背面（52）去除模塑料（66）和层压材料（44），以形成露出背面（52）的开口（78）。 导电材料（84,88）被放置在开口（78）中并且用作IC模具（48）的散热器和/或接地。

公开(公告)号：US06951801B2

公开(公告)日：2005-10-04

申请号：US10351798

申请日：2003-01-27

申请人： Scott K. Pozder ,  Trent S. Uehling ,  Lakshmi N. Ramanathan

发明人： Scott K. Pozder ,  Trent S. Uehling ,  Lakshmi N. Ramanathan

IPC分类号： H01L20060101 ,  H01L21/20 ,  H01L21/301 ,  H01L21/304 ,  H01L21/3213 ,  H01L21/78

CPC分类号： H01L21/78 ,  H01L21/3043 ,  H01L21/32134

摘要： A process for removing metal from a scribe area of a semiconductor wafer. The metal removed may include exposed metal in a saw path of the scribe area and the metal in a crack stop trench of the scribe area. In one example, copper is removed from the scribe area by wet etching the wafer. In one example, the wet etching process is performed after the removal of an exposed barrier adhesion layer on the wafer surface. Removal of the metal in the saw path may reduce the amount of metal buildup on a saw blade during singulation of the die areas of a wafer.

摘要翻译： 一种用于从半导体晶片的划线区域去除金属的工艺。 去除的金属可以包括划线区域的锯路径中的暴露的金属和划线区域的裂纹停止槽中的金属。 在一个实例中，通过湿法蚀刻晶片从刻划区域去除铜。 在一个实例中，在去除晶片表面上的暴露的阻挡粘附层之后执行湿蚀刻工艺。 锯切路径中的金属的去除可以减少在晶片的模具区域的分割期间在锯片上的金属积累量。

公开(公告)号：US08803302B2

公开(公告)日：2014-08-12

申请号：US13484664

申请日：2012-05-31

申请人： Lakshminarayan Viswanathan ,  Lakshmi N. Ramanathan ,  Audel A. Sanchez ,  Fernando A. Santos

发明人： Lakshminarayan Viswanathan ,  Lakshmi N. Ramanathan ,  Audel A. Sanchez ,  Fernando A. Santos

IPC分类号： H01L21/00

CPC分类号： H01L23/49568 ,  H01L21/4825 ,  H01L21/4882 ,  H01L21/561 ,  H01L21/568 ,  H01L23/04 ,  H01L23/3107 ,  H01L23/3677 ,  H01L23/49506 ,  H01L23/49531 ,  H01L23/49541 ,  H01L23/49575 ,  H01L23/49582 ,  H01L24/32 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A packaged semiconductor device may include a termination surface having terminations configured as leadless interconnects to be surface mounted to a printed circuit board. A first flange has a first surface and a second surface. The first surface provides a first one of the terminations, and the second surface is opposite to the first surface. A second flange also has a first surface and a second surface, with the first surface providing a second one of the terminations, and the second surface is opposite to the first surface. A die is mounted to the second surface of the first flange with a material having a melting point in excess of 240° C. An electrical interconnect extends between the die and the second surface of the second flange opposite the termination surface, such that the electrical interconnect, first flange and second flange are substantially housed within a body.

摘要翻译： 封装的半导体器件可以包括终端表面，其终端被配置为表面安装到印刷电路板的无引线互连。 第一凸缘具有第一表面和第二表面。 第一表面提供第一个终端，第二表面与第一表面相对。 第二凸缘还具有第一表面和第二表面，其中第一表面提供端接件中的第二表面，并且第二表面与第一表面相对。 模具通过熔点超过240℃的材料安装到第一凸缘的第二表面上。电互连件在模具与第二凸缘的与端接表面相对的第二表面之间延伸，使得电气 互连，第一凸缘和第二凸缘基本上容纳在主体内。

公开(公告)号：US07950144B2

公开(公告)日：2011-05-31

申请号：US12112489

申请日：2008-04-30

申请人： Lakshmi N. Ramanathan ,  George R. Leal ,  Douglas G. Mitchell ,  Betty H. Yeung

发明人： Lakshmi N. Ramanathan ,  George R. Leal ,  Douglas G. Mitchell ,  Betty H. Yeung

IPC分类号： H05K3/30

CPC分类号： H01L21/67288 ,  H01L23/16 ,  H01L23/3107 ,  H01L23/562 ,  H01L24/96 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/3025 ,  H01L2924/3511 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49133 ,  Y10T29/49139 ,  Y10T29/49155 ,  Y10T29/49171 ,  H01L2924/00

摘要： A method is disclosed for controlling warpage in an integrated electronic panel assembly including a plurality of die embedded within an encapsulant. The method comprises determining a number of build-up layers required for the integrated panel assembly. Each build-up layer contributes an amount of concavity to the integrated electronic panel assembly. A level of global convex warpage on the integrated panel assembly is then predicted, wherein the global convex warpage is provided by the presence of an embedded ground plane (EGP) alone within the integrated panel assembly and in the absence of any build-up layers. The embedded ground plane includes openings therein for accepting at least one die within a corresponding opening and it contributes a fixed amount of global convex warpage. An amount of local convex warpage to be introduced into the integrated electronic panel assembly is then determined, which together with the fixed amount of global convex warpage provides a combined convex warpage to the integrated electronic panel assembly. Accordingly, the global and local convex warpage counteract the concavity to be introduced subsequently by a build-up layer processing and is sufficient to enable subsequent planar processing of a completed integrated electronic panel assembly.

摘要翻译： 公开了一种用于控制集成电子面板组件中的翘曲的方法，其包括嵌入密封剂内的多个管芯。 该方法包括确定集成面板组件所需的累积层数。 每个积层对于集成电子面板组件贡献一定量的凹陷。 然后预测集成面板组件上的全局凸起翘曲的水平，其中全局凸起翘曲由嵌入式接地平面（EGP）单独存在于集成面板组件内并且在没有任何积聚层的情况下提供。 嵌入式接地平面包括用于在相应的开口内接受至少一个模具的开口，并且其有助于固定量的全局凸起翘曲。 然后确定要引入集成电子面板组件的局部凸起翘曲的量，其与固定量的全局凸起翘曲一起提供到集成电子面板组件的组合凸起翘曲。 因此，全局和局部凸起翘曲抵消随后通过积层处理引入的凹面，并且足以使得完整的集成电子面板组件能够进行后续的平面处理。

公开(公告)号：US07812448B2

公开(公告)日：2010-10-12

申请号：US11501096

申请日：2006-08-07

申请人： Lakshmi N. Ramanathan ,  Tien Yu T. Lee ,  Jinbang Tang

发明人： Lakshmi N. Ramanathan ,  Tien Yu T. Lee ,  Jinbang Tang

IPC分类号： H01L23/48

CPC分类号： H01L24/10 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05026 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05164 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2924/00014

摘要： An electronic device can include an interconnect level (16) including a bonding pad region (110). An insulating layer (18) can overlie the interconnect level (16) and include an opening (112, 24) over the bonding pad region (110). In one embodiment, a conductive stud (34) can lie within the opening (112, 24) and can be substantially encapsulated. In another embodiment, the electronic device can include a barrier layer (22) lying along a side and a bottom of the opening (112, 24) and a conductive stud (34) lying within the opening (112, 24). The conductive stud (34) can substantially fill the opening (112, 24). A majority of the conductive stud (34) can lie within the opening (112, 24). In still another embodiment, a process for forming an electronic device can include forming a conductive stud (34) within the opening (112, 24) wherein the conductive stud (34) lies substantially completely within the opening (112, 24). The process can also include forming a second barrier layer (52) overlying the conductive stud (34).

摘要翻译： 电子设备可以包括包括焊盘区域（110）的互连级（16）。 绝缘层（18）可以覆盖互连层（16）并且包括在焊盘区域（110）上方的开口（112,24）。 在一个实施例中，导电柱（34）可以位于开口（112,24）内，并且可以被基本封装。 在另一个实施例中，电子设备可以包括位于开口（112,24）的侧面和底部以及位于开口（112,24）内的导电柱）的阻挡层（22）。 导电螺柱（34）可以基本上填充开口（112,24）。 导电螺柱（34）的大部分可以位于开口（112,24）内。 在另一个实施例中，用于形成电子设备的工艺可以包括在开口（112,24）内形成导电柱（34），其中导电螺柱（34）基本上完全位于开口（112,24）内。 该工艺还可以包括形成覆盖在导电螺柱（34）上的第二阻挡层（52）。

公开(公告)号：US20090271980A1

公开(公告)日：2009-11-05

申请号：US12112489

申请日：2008-04-30

申请人： Lakshmi N. Ramanathan ,  George R. Leal ,  Douglas G. Mitchell ,  Betty H. Yeung

发明人： Lakshmi N. Ramanathan ,  George R. Leal ,  Douglas G. Mitchell ,  Betty H. Yeung

IPC分类号： H05K7/02

CPC分类号： H01L21/67288 ,  H01L23/16 ,  H01L23/3107 ,  H01L23/562 ,  H01L24/96 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/3025 ,  H01L2924/3511 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49133 ,  Y10T29/49139 ,  Y10T29/49155 ,  Y10T29/49171 ,  H01L2924/00

摘要： A method is disclosed for controlling warpage in an integrated electronic panel assembly including a plurality of die embedded within an encapsulant. The method comprises determining a number of build-up layers required for the integrated panel assembly. Each build-up layer contributes an amount of concavity to the integrated electronic panel assembly. A level of global convex warpage on the integrated panel assembly is then predicted, wherein the global convex warpage is provided by the presence of an embedded ground plane (EGP) alone within the integrated panel assembly and in the absence of any build-up layers. The embedded ground plane includes openings therein for accepting at least one die within a corresponding opening and it contributes a fixed amount of global convex warpage. An amount of local convex warpage to be introduced into the integrated electronic panel assembly is then determined, which together with the fixed amount of global convex warpage provides a combined convex warpage to the integrated electronic panel assembly. Accordingly, the global and local convex warpage counteract the concavity to be introduced subsequently by a build-up layer processing and is sufficient to enable subsequent planar processing of a completed integrated electronic panel assembly.

摘要翻译： 公开了一种用于控制集成电子面板组件中的翘曲的方法，其包括嵌入密封剂内的多个管芯。 该方法包括确定集成面板组件所需的累积层数。 每个积层对于集成电子面板组件贡献一定量的凹陷。 然后预测集成面板组件上的全局凸起翘曲的水平，其中全局凸起翘曲由嵌入式接地平面（EGP）单独存在于集成面板组件内并且在没有任何积聚层的情况下提供。 嵌入式接地平面包括用于在相应的开口内接受至少一个模具的开口，并且其有助于固定量的全局凸起翘曲。 然后确定要引入集成电子面板组件的局部凸起翘曲的量，其与固定量的全局凸起翘曲一起提供到集成电子面板组件的组合凸起翘曲。 因此，全局和局部凸起翘曲抵消随后通过积层处理引入的凹面，并且足以使得完整的集成电子面板组件能够进行后续的平面处理。

公开(公告)号：US20080029887A1

公开(公告)日：2008-02-07

申请号：US11501096

申请日：2006-08-07

申请人： Lakshmi N. Ramanathan ,  Tien Yu T. Lee ,  Jinbang Tang

发明人： Lakshmi N. Ramanathan ,  Tien Yu T. Lee ,  Jinbang Tang

IPC分类号： H01L23/48

CPC分类号： H01L24/10 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05026 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05164 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2924/00014

摘要： An electronic device can include an interconnect level (16) including a bonding pad region (110). An insulating layer (18) can overlie the interconnect level (16) and include an opening (112, 24) over the bonding pad region (110). In one embodiment, a conductive stud (34) can lie within the opening (112, 24) and can be substantially encapsulated. In another embodiment, the electronic device can include a barrier layer (22) lying along a side and a bottom of the opening (112, 24) and a conductive stud (34) lying within the opening (112, 24). The conductive stud (34) can substantially fill the opening (112, 24). A majority of the conductive stud (34) can lie within the opening (112, 24). In still another embodiment, a process for forming an electronic device can include forming a conductive stud (34) within the opening (112, 24) wherein from a top view, the conductive stud (34) lies substantially completely within the opening (112, 24). The process can also include forming a second barrier layer (52) overlying the conductive stud (34).

摘要翻译： 电子设备可以包括包括焊盘区域（110）的互连级（16）。 绝缘层（18）可以覆盖互连层（16）并且包括在焊盘区域（110）上方的开口（112,24）。 在一个实施例中，导电柱（34）可以位于开口（112,24）内，并且可以被基本封装。 在另一个实施例中，电子设备可以包括位于开口（112,24）的侧面和底部以及位于开口（112,24）内的导电柱）的阻挡层（22）。 导电螺柱（34）可以基本上填充开口（112,24）。 导电螺柱（34）的大部分可以位于开口（112,24）内。 在另一个实施例中，用于形成电子设备的方法可以包括在开口（112,24）内形成导电柱（34），其中从顶视图，导电柱（34）基本上完全位于开口（112,24）内， 24）。 该工艺还可以包括形成覆盖在导电螺柱（34）上的第二阻挡层（52）。