Invention Grant
- Patent Title: Layout methods of integrated circuits having unit MOS devices
- Patent Title (中): 具有单位MOS器件的集成电路的布局方法
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Application No.: US11807654Application Date: 2007-05-30
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Publication No.: US08237201B2Publication Date: 2012-08-07
- Inventor: Harry Chuang , Kong-Beng Thei , Jen-Bin Hsu , Chung Long Cheng , Mong Song Liang
- Applicant: Harry Chuang , Kong-Beng Thei , Jen-Bin Hsu , Chung Long Cheng , Mong Song Liang
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater & Matsil, L.L.P.
- Main IPC: H01L27/118
- IPC: H01L27/118

Abstract:
A semiconductor structure includes an array of unit metal-oxide-semiconductor (MOS) devices arranged in a plurality of rows and a plurality of columns is provided. Each of the unit MOS devices includes an active region laid out in a row direction and a gate electrode laid out in a column direction. The semiconductor structure further includes a first unit MOS device in the array and a second unit MOS device in the array, wherein active regions of the first and the second unit MOS devices have different conductivity types.
Public/Granted literature
- US20080296691A1 Layout methods of integrated circuits having unit MOS devices Public/Granted day:2008-12-04
Information query
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