Invention Grant
US08241928B2 Test structure and method for detecting charge effects during semiconductor processing
有权
用于在半导体处理期间检测电荷效应的测试结构和方法
- Patent Title: Test structure and method for detecting charge effects during semiconductor processing
- Patent Title (中): 用于在半导体处理期间检测电荷效应的测试结构和方法
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Application No.: US12777858Application Date: 2010-05-11
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Publication No.: US08241928B2Publication Date: 2012-08-14
- Inventor: Ming-Hsiu Lee , Chao-I Wu , Ming-Chang Kuo
- Applicant: Ming-Hsiu Lee , Chao-I Wu , Ming-Chang Kuo
- Applicant Address: TW
- Assignee: Macronix International Co., Ltd.
- Current Assignee: Macronix International Co., Ltd.
- Current Assignee Address: TW
- Agency: Baker & McKenzie LLP
- Main IPC: H01L21/66
- IPC: H01L21/66
Abstract:
A semiconductor process test structure comprises an electrode, a charge-trapping layer, and a diffusion region. The test structure is a capacitor-like structure in which the charge-trapping layer will trap charges during various processing steps. Gate-induced drain leakage (GIDL) measurement techniques can then be used to characterize the charging status of the test structure.
Public/Granted literature
- US20100221851A1 TEST STRUCTURE AND METHOD FOR DETECTING CHARGE EFFECTS DURING SEMICONDUCTOR PROCESSING Public/Granted day:2010-09-02
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