公开(公告)号：US08467238B2

公开(公告)日：2013-06-18

申请号：US12946636

申请日：2010-11-15

申请人： Chao-I Wu

发明人： Chao-I Wu

IPC分类号： G11C11/00

CPC分类号： G11C13/0004 ,  G11C13/0033 ,  G11C13/0035

摘要： The control circuit performs a reset operation and a set operation that change the resistance states of phase change memory cells of the array. The control circuit changes at least one parameter, of at least one of the reset operation and the set operation for future operations. This change is responsive to an indicator of degraded memory state retention of the array.

摘要翻译： 控制电路进行改变阵列的相变存储单元的电阻状态的复位动作和设定动作。 控制电路至少改变一个参数，至少一个复位操作和设置操作中的一个参数用于将来的操作。 该更改响应于阵列的内存状态保留降级的指示符。

公开(公告)号：US08432745B2

公开(公告)日：2013-04-30

申请号：US13184189

申请日：2011-07-15

申请人： Chao-I Wu

发明人： Chao-I Wu

IPC分类号： G11C16/00

CPC分类号： H01L21/28282 ,  G11C16/0475 ,  G11C16/0491 ,  H01L27/11568 ,  H01L29/7923

摘要： A non-volatile VG memory array employing memory semiconductor cells capable of storing two bits of information having a non-conducting charge trapping dielectric, such as silicon nitride, layered in associating with at least one electrical insulating layer, such as an oxide, is disclosed. Bit lines of the memory array are capable of transmitting positive voltage to reach the source/drain regions of the memory cells of the array. A method that includes the hole injection erasure of the memory cells of the array that lowers the voltage threshold of the memory cells to a value lower than the initial voltage threshold of the cells is disclosed. The hole injection induced lower voltage threshold reduces the second bit effect such that the window of operation between the programmed and un-programmed voltage thresholds of the bits is widened. The programming and read steps reduce leakage current of the memory cells in the array.

摘要翻译： 公开了一种采用存储器半导体单元的非易失性VG存储器阵列，该存储器半导体单元能够存储与至少一个电绝缘层（例如氧化物）相结合的分层的非导电电荷俘获电介质（例如氮化硅）的两比特信息。 。 存储器阵列的位线能够传输正电压以到达阵列的存储器单元的源极/漏极区域。 公开了一种方法，其包括将阵列的存储单元的空穴注入擦除将存储单元的电压阈值降低到低于单元的初始电压阈值的值。 空穴注入诱导的较低电压阈值降低了第二位效应，使得位的编程和未编程电压阈值之间的操作窗口变宽。 编程和读取步骤减少阵列中存储单元的泄漏电流。

公开(公告)号：US08378382B2

公开(公告)日：2013-02-19

申请号：US11027807

申请日：2004-12-30

申请人： Chao-I Wu ,  Ming Hsiu Lee

发明人： Chao-I Wu ,  Ming Hsiu Lee

IPC分类号： H01L29/66 ,  H01L29/861

CPC分类号： H01L27/0814 ,  H01L27/1021 ,  H01L29/8613

摘要： A semiconductor device having high-aspect-ratio PN-junctions is provided. The semiconductor device includes a conducting layer. The semiconductor device further includes a plurality of first doped regions formed over the conducting layer. The sidewalls of the doped regions are doped to form PN-junctions. The semiconductor device also includes a plurality of second doped regions over the first doped regions.

摘要翻译： 提供了具有高纵横比PN结的半导体器件。 半导体器件包括导电层。 半导体器件还包括形成在导电层上的多个第一掺杂区域。 掺杂区域的侧壁被掺杂以形成PN结。 半导体器件还包括在第一掺杂区域上的多个第二掺杂区域。

公开(公告)号：US08363463B2

公开(公告)日：2013-01-29

申请号：US12729837

申请日：2010-03-23

申请人： Yen-Hao Shih ,  Huai-Yu Cheng ,  Chieh-Fang Chen ,  Chao-I Wu ,  Ming Hsiu Lee ,  Hsiang-Lan Lung ,  Matthew J. Breitwisch ,  Simone Raoux ,  Chung H Lam

发明人： Yen-Hao Shih ,  Huai-Yu Cheng ,  Chieh-Fang Chen ,  Chao-I Wu ,  Ming Hsiu Lee ,  Hsiang-Lan Lung ,  Matthew J. Breitwisch ,  Simone Raoux ,  Chung H Lam

IPC分类号： G11C11/00

CPC分类号： H01L45/1625 ,  G11C13/0004 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1641

摘要： A phase change memory device with a memory element including a basis phase change material, such as a chalcogenide, and one or more additives, where the additive or additives have a non-constant concentration profile along an inter-electrode current path through a memory element. The use of “non-constant” concentration profiles for additives enables doping the different zones with different materials and concentrations, according to the different crystallographic, thermal and electrical conditions, and different phase transition conditions.

摘要翻译： 一种具有存储元件的相变存储器件，该存储元件包括诸如硫族化物的基本相变材料和一种或多种添加剂，其中所述添加剂或添加剂沿着穿过存储元件的电极间电流路径具有非恒定浓度分布 。 根据不同的晶体学，热学和电学条件以及不同的相变条件，使用非恒定浓度分布的添加剂可以使用不同的材料和浓度掺杂不同的区域。

公开(公告)号：US08295094B2

公开(公告)日：2012-10-23

申请号：US13168536

申请日：2011-06-24

申请人： Chao-I Wu

发明人： Chao-I Wu

IPC分类号： G11C11/34

CPC分类号： H01L21/28282 ,  G11C16/0408 ,  G11C16/0466 ,  G11C16/107 ,  H01L29/78654 ,  H01L29/792

摘要： A method of operating a memory cell for 3D array of this invention is described as follows. Carriers of a first type are injected into a charge storage layer of the memory cell by applying a double-side biased (DSB) voltage to double sides of the memory cell. Carriers of a second type are injected into the charge storage layer by applying FN voltages.

摘要翻译： 本发明的3D阵列的存储单元的操作方法如下。 通过在存储单元的双面施加双面偏置（DSB）电压将第一类型的载体注入存储单元的电荷存储层。 通过施加FN电压将第二类型的载体注入电荷存储层。

公开(公告)号：US08263464B2

公开(公告)日：2012-09-11

申请号：US12791508

申请日：2010-06-01

申请人： Chao I Wu

发明人： Chao I Wu

IPC分类号： H01L21/336

CPC分类号： H01L27/112 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/11206 ,  H01L27/11286 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11578

摘要： A memory structure that combines embedded flash memory and PPROM. The PPROM can be used as a memory structure. The flash memory can be used, e.g., as air replacement cells or back up memory, or additional memory cells. The PPROM cells are stacked on top of the flash memory cells and the PPROM density can be increased by implementing three-dimensional PPROM structures.

摘要翻译： 结合嵌入式闪存和PPROM的内存结构。 PPROM可以用作存储器结构。 闪存可用于例如空气替换单元或备用存储器或附加存储器单元。 PPROM单元堆叠在闪存单元的顶部，并且可以通过实现三维PPROM结构来增加PPROM密度。

公开(公告)号：US20120120723A1

公开(公告)日：2012-05-17

申请号：US12946636

申请日：2010-11-15

申请人： Chao-I Wu

发明人： Chao-I Wu

IPC分类号： G11C11/21

CPC分类号： G11C13/0004 ,  G11C13/0033 ,  G11C13/0035

摘要： The control circuit performs a reset operation and a set operation that change the resistance states of phase change memory cells of the array. The control circuit changes at least one parameter, of at least one of the reset operation and the set operation for future operations. This change is responsive to an indicator of degraded memory state retention of the array.

摘要翻译： 控制电路进行改变阵列的相变存储单元的电阻状态的复位动作和设定动作。 控制电路至少改变一个参数，至少一个复位操作和设置操作中的一个参数用于将来的操作。 该变化响应于阵列的内存状态保持降低的指示符。

公开(公告)号：US20110317480A1

公开(公告)日：2011-12-29

申请号：US12823508

申请日：2010-06-25

申请人： HSIANG-LAN LUNG ,  Ming Hsiu Lee ,  Yen-Hao Shih ,  Tien-Yen Wang ,  Chao-I Wu

发明人： HSIANG-LAN LUNG ,  Ming Hsiu Lee ,  Yen-Hao Shih ,  Tien-Yen Wang ,  Chao-I Wu

IPC分类号： G11C11/00 ,  H01L21/06

CPC分类号： G11C13/0004 ,  G11C11/5678 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0092

摘要： An integrated circuit phase change memory can be pre-coded by inducing a first resistance state in some cells and the memory, and a second resistance state and some other cells in the memory to represent a data set. The integrated circuit phase change memory is mounted on a substrate after coding the data set. After mounting the integrated circuit phase change memory, the data set is read by sensing the first and second resistance states, and changing cells in the first resistance state to a third resistance state and changing cells in the second resistance state to a fourth resistance state. The first and second resistance states maintain a sensing margin after solder bonding or other thermal cycling process. The third and fourth resistance states are characterized by the ability to cause a transition using higher speed and lower power, suitable for a mission function of a circuit.

摘要翻译： 集成电路相变存储器可以通过在一些单元和存储器中引起第一电阻状态以及存储器中的第二电阻状态以及存储器中的一些其他单元来表示数据集而被预编码。 在对数据集进行编码之后，将集成电路相变存储器安装在基板上。 在安装集成电路相变存储器之后，通过感测第一和第二电阻状态以及将第一电阻状态下的单元改变为第三电阻状态并将第二电阻状态的单元改变为第四电阻状态来读取数据组。 第一和第二电阻状态在焊接或其他热循环过程之后保持感测裕度。 第三和第四电阻状态的特征在于能够使用更高速度和更低功率的转换，适用于电路的任务功能。

公开(公告)号：US20110255349A1

公开(公告)日：2011-10-20

申请号：US13168536

申请日：2011-06-24

申请人： Chao-I Wu

发明人： Chao-I Wu

IPC分类号： G11C16/10

CPC分类号： H01L21/28282 ,  G11C16/0408 ,  G11C16/0466 ,  G11C16/107 ,  H01L29/78654 ,  H01L29/792

摘要： A method of operating a memory cell for 3D array of this invention is described as follows. Carriers of a first type are injected into a charge storage layer of the memory cell by applying a double-side biased (DSB) voltage to double sides of the memory cell. Carriers of a second type are injected into the charge storage layer by applying FN voltages.

摘要翻译： 本发明的3D阵列的存储单元的操作方法如下。 通过在存储单元的双面施加双面偏置（DSB）电压将第一类型的载体注入存储单元的电荷存储层。 通过施加FN电压将第二类型的载体注入电荷存储层。

公开(公告)号：US07986564B2

公开(公告)日：2011-07-26

申请号：US12233904

申请日：2008-09-19

申请人： Chao-I Wu

发明人： Chao-I Wu

IPC分类号： G11C16/04

CPC分类号： H01L21/28282 ,  G11C16/0475 ,  G11C16/0491 ,  H01L27/11568 ,  H01L29/7923

摘要： A non-volatile VG memory array employing memory semiconductor cells capable of storing two bits of information having a non-conducting charge trapping dielectric, such as silicon nitride, layered in associating with at least one electrical insulating layer, such as an oxide, is disclosed. Bit lines of the memory array are capable of transmitting positive voltage to reach the source/drain regions of the memory cells of the array. A method that includes the hole injection erasure of the memory cells of the array that lowers the voltage threshold of the memory cells to a value lower than the initial voltage threshold of the cells is disclosed. The hole injection induced lower voltage threshold reduces the second bit effect such that the window of operation between the programmed and un-programmed voltage thresholds of the bits is widened. The programming and read steps reduce leakage current of the memory cells in the array.

摘要翻译： 公开了一种采用存储器半导体单元的非易失性VG存储器阵列，该存储器半导体单元能够存储与至少一个电绝缘层（例如氧化物）相结合的分层的非导电电荷俘获电介质（例如氮化硅）的两比特信息。 。 存储器阵列的位线能够传输正电压以到达阵列的存储器单元的源极/漏极区域。 公开了一种方法，其包括将阵列的存储单元的空穴注入擦除将存储单元的电压阈值降低到低于单元的初始电压阈值的值。 空穴注入诱导的较低电压阈值降低了第二位效应，使得位的编程和未编程电压阈值之间的操作窗口变宽。 编程和读取步骤减少阵列中存储单元的泄漏电流。