发明授权
US08258548B2 Semiconductor device with gate level including four transistors of first type and four transistors of second type separated by non-diffusion region with restricted gate contact placement over separating non-diffusion region
有权
具有栅极电平的半导体器件包括第一类型的四个晶体管和第二类型的四个晶体管，由非扩散区域隔开，并且在分离非扩散区域上具有限制的栅极接触放置
- 专利标题： Semiconductor device with gate level including four transistors of first type and four transistors of second type separated by non-diffusion region with restricted gate contact placement over separating non-diffusion region
- 专利标题（中）： 具有栅极电平的半导体器件包括第一类型的四个晶体管和第二类型的四个晶体管，由非扩散区域隔开，并且在分离非扩散区域上具有限制的栅极接触放置
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申请号： US12571998申请日： 2009-10-01
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公开(公告)号： US08258548B2公开(公告)日： 2012-09-04
- 发明人: Scott T. Becker , Michael C. Smayling
- 申请人： Scott T. Becker , Michael C. Smayling
- 申请人地址： US CA Los Gatos
- 专利权人： Tela Innovations, Inc.
- 当前专利权人： Tela Innovations, Inc.
- 当前专利权人地址： US CA Los Gatos
- 代理机构： Martine Penilla Group, LLP
- 主分类号： H01L27/10
- IPC分类号： H01L27/10
摘要：
A cell of a semiconductor device includes a substrate portion formed to include a plurality of diffusion regions, including at least one p-type diffusion region and at least one n-type diffusion region separated from each other by one or more non-active regions. The cell includes a gate electrode level including a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level is fabricated from a respective originating rectangular-shaped layout feature. Some of the conductive features form respective PMOS and/or NMOS transistor devices. A number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the gate electrode level of the cell. The cell also includes a number of interconnect levels formed above the gate electrode level.
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