Invention Grant
- Patent Title: Pattern generating method, method of manufacturing semiconductor device, and recording medium
- Patent Title (中): 图案生成方法,制造半导体器件的方法和记录介质
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Application No.: US12705640Application Date: 2010-02-15
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Publication No.: US08266552B2Publication Date: 2012-09-11
- Inventor: Takafumi Taguchi , Toshiya Kotani , Michiya Takimoto , Fumiharu Nakajima , Ryota Aburada , Hiromitsu Mashita , Katsumi Iyanagi , Chikaaki Kodama
- Applicant: Takafumi Taguchi , Toshiya Kotani , Michiya Takimoto , Fumiharu Nakajima , Ryota Aburada , Hiromitsu Mashita , Katsumi Iyanagi , Chikaaki Kodama
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.
- Priority: JP2009-070976 20090323
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G06F19/00 ; G05B13/04

Abstract:
Pattern formation simulations are performed based on design layout data subjected to OPC processing with a plurality of process parameters set in process conditions. A worst condition of the process conditions is calculated based on risk points extracted from simulation results. The design layout data or the OPC processing is changed such that when a pattern is formed under the worst condition based on the changed design layout data or the changed OPC processing a number of the risk points or a risk degree of the risk points of the pattern is smaller than the simulation result.
Public/Granted literature
- US20100241261A1 PATTERN GENERATING METHOD, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND COMPUTER PROGRAM PRODUCT Public/Granted day:2010-09-23
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