发明授权
- 专利标题: High speed memory simulation
- 专利标题(中): 高速内存模拟
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申请号: US12020871申请日: 2008-01-28
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公开(公告)号: US08275597B1公开(公告)日: 2012-09-25
- 发明人: Chanhee Oh , John F. Croix , Curtis L. Ratzlaff , Ramon D. Acosta
- 申请人: Chanhee Oh , John F. Croix , Curtis L. Ratzlaff , Ramon D. Acosta
- 申请人地址: US CA San Jose
- 专利权人: Cadence Design Systems, Inc.
- 当前专利权人: Cadence Design Systems, Inc.
- 当前专利权人地址: US CA San Jose
- 代理机构: Holland & Knight LLP
- 代理商 Brian J. Colandreo, Esq.; Mark H. Whittenberger, Esq.
- 主分类号: G06F17/50
- IPC分类号: G06F17/50 ; G06F9/54 ; G06F13/10 ; G06F13/12 ; G06G7/62 ; G06G7/54
摘要:
In one embodiment, a method comprises creating a simulation model for a column of bit cells in a memory, simulating the simulation model to generate a result; and displaying the result for a user. Each of the bit cells in the column is coupled to a different wordline, and the simulation model comprises one or more linear elements in place of a nonlinear element in each bit cell that is coupled to an inactive wordline. The one or more linear elements approximate a behavior of the nonlinear element while the wordline is inactive. A computer accessible storage medium storing a simulator that implements the method is contemplated, and the simulator itself is also contemplated, in various embodiments.
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