公开(公告)号：US08275597B1

公开(公告)日：2012-09-25

申请号：US12020871

申请日：2008-01-28

申请人： Chanhee Oh ,  John F. Croix ,  Curtis L. Ratzlaff ,  Ramon D. Acosta

发明人： Chanhee Oh ,  John F. Croix ,  Curtis L. Ratzlaff ,  Ramon D. Acosta

IPC分类号： G06F17/50 ,  G06F9/54 ,  G06F13/10 ,  G06F13/12 ,  G06G7/62 ,  G06G7/54

CPC分类号： G06F17/5036 ,  G06F2217/84

摘要： In one embodiment, a method comprises creating a simulation model for a column of bit cells in a memory, simulating the simulation model to generate a result; and displaying the result for a user. Each of the bit cells in the column is coupled to a different wordline, and the simulation model comprises one or more linear elements in place of a nonlinear element in each bit cell that is coupled to an inactive wordline. The one or more linear elements approximate a behavior of the nonlinear element while the wordline is inactive. A computer accessible storage medium storing a simulator that implements the method is contemplated, and the simulator itself is also contemplated, in various embodiments.

摘要翻译： 在一个实施例中，一种方法包括为存储器中的一列位单元创建仿真模型，模拟仿真模型以产生结果; 并显示用户的结果。 列中的每个位单元耦合到不同的字线，并且仿真模型包括一个或多个线性元件，代替耦合到非活动字线的每个位单元中的非线性元件。 一个或多个线性元素近似非线性元素的行为，而字线是无效的。 考虑了存储实现该方法的模拟器的计算机可访问存储介质，并且在各种实施例中也可以设想模拟器本身。

公开(公告)号：US06766506B1

公开(公告)日：2004-07-20

申请号：US09707757

申请日：2000-11-07

申请人： Curtis L. Ratzlaff ,  John F. Croix ,  Robert Jones

发明人： Curtis L. Ratzlaff ,  John F. Croix ,  Robert Jones

IPC分类号： G06F1750

CPC分类号： G06F17/5036

摘要： Systems and methods are described for a circuit interconnect model compiler. A method includes providing extraction data from an interconnect; reading a dataset from said extraction data from said interconnect; reducing said dataset to form a model; evaluating said model for a set of conditions to obtain a solution; and writing said solution to an application. The systems and methods provide advantages in that the speed, reliability and accuracy of the design process are improved and the affect of circuit interconnects is taken into account.

摘要翻译： 为电路互连模型编译器描述了系统和方法。 一种方法包括从互连提供提取数据; 从所述互连的所述提取数据读取数据集; 减少数据集形成一个模型; 评估所述模型的一组条件以获得解决方案; 并将该解决方案写入应用程序。 这些系统和方法提供了优点，即提高了设计过程的速度，可靠性和精度，并考虑了电路互连的影响。

公开(公告)号：US07970591B1

公开(公告)日：2011-06-28

申请号：US12169277

申请日：2008-07-08

申请人： Curtis L. Ratzlaff

发明人： Curtis L. Ratzlaff

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： In one embodiment, a method for simulating an electric circuit that is represented as one or more partitions, each partition comprising a plurality of constituents representing portions of the circuit, wherein at least one of the constituents is a variable constituent for which the corresponding portion of the electronic circuit includes non-linear behavior, comprises: determining a first matrix for the variable constituent, wherein the first matrix describes a system of equations that represents a behavior of the variable constituent; determining a second matrix for the partition, wherein the second matrix permits calculation of short circuit currents from open circuit voltages according to a node tearing analysis method; and simulating a timestep of the simulation, the simulating comprising iteratively solving a state of the partition using successive guesses of the state of the variable constituent, wherein each iteration comprises solving the variable constituent independently to generate the open circuit voltages using the first matrix, applying the second matrix to determine the short circuit currents, and resolving the variable constituent with the short circuit currents applied and the forcing functions disabled; converging to a solution during the iteratively solving; and solving the partition state for the timestep responsive to the convergence.

摘要翻译： 在一个实施例中，一种用于模拟被表示为一个或多个分区的电路的方法，每个分区包括表示电路部分的多个组成部分，其中至少一个组成部分是可变成分， 所述电子电路包括非线性行为，包括：确定所述可变成分的第一矩阵，其中所述第一矩阵描述表示所述可变成分的行为的方程组; 确定所述分区的第二矩阵，其中所述第二矩阵允许根据节点撕裂分析方法计算来自开路电压的短路电流; 以及模拟所述模拟的时间步长，所述模拟包括使用所述可变构件的状态的连续猜测迭代地求解所述分区的状态，其中每次迭代包括独立地求解所述可变成分以使用所述第一矩阵产生所述开路电压，应用 确定短路电流的第二矩阵，并且利用施加的短路电流来解决可变成分并且强制功能被禁用; 在迭代求解过程中收敛到解; 并响应于收敛来求解时间步长的分区状态。

公开(公告)号：US5379231A

公开(公告)日：1995-01-03

申请号：US891649

申请日：1992-05-29

申请人： Lawrence T. Pillage ,  Curtis L. Ratzlaff ,  Nanda Gopal

发明人： Lawrence T. Pillage ,  Curtis L. Ratzlaff ,  Nanda Gopal

IPC分类号： G06F17/50 ,  G06F15/60

CPC分类号： G06F17/5036

摘要： A method and apparatus for simulating a microelectronic circuit or system includes the storing of a microelectronic circuit or system representation in a computer and then transforming the representation into an equivalent DC circuit containing resistive, capacitive and inductive elements. Then, a directed graph of the DC equivalent circuit is generated and a spanning tree is constructed therefrom. The spanning tree is then actually or virtually traversed to obtain multiple generations of circuit moments. The moments are then used to calculate the poles and residues for a given node and generate an approximate model of the circuit's transient response at that node. Moment shifting is used to provide for a stable approximate model. The actual residues corresponding to the coefficients of the time domain representation for the model can be calculated using the first q-1 moments. This constitutes a partial-Pade approximation.

摘要翻译： 用于模拟微电子电路或系统的方法和装置包括在计算机中存储微电子电路或系统表示，然后将表示变换为包含电阻，电容和电感元件的等效DC电路。 然后，产生DC等效电路的有向图，并从其构建生成树。 然后实际或虚拟地遍历生成树以获得多代电路时刻。 然后将时刻用于计算给定节点的极点和残差，并生成电路在该节点处的瞬态响应的近似模型。 瞬时转换用于提供稳定的近似模型。 可以使用第一个q-1时刻计算与模型的时域表示的系数相对应的实际残差。 这构成了部分Padé近似。