公开(公告)号：US08275597B1

公开(公告)日：2012-09-25

申请号：US12020871

申请日：2008-01-28

申请人： Chanhee Oh ,  John F. Croix ,  Curtis L. Ratzlaff ,  Ramon D. Acosta

发明人： Chanhee Oh ,  John F. Croix ,  Curtis L. Ratzlaff ,  Ramon D. Acosta

IPC分类号： G06F17/50 ,  G06F9/54 ,  G06F13/10 ,  G06F13/12 ,  G06G7/62 ,  G06G7/54

CPC分类号： G06F17/5036 ,  G06F2217/84

摘要： In one embodiment, a method comprises creating a simulation model for a column of bit cells in a memory, simulating the simulation model to generate a result; and displaying the result for a user. Each of the bit cells in the column is coupled to a different wordline, and the simulation model comprises one or more linear elements in place of a nonlinear element in each bit cell that is coupled to an inactive wordline. The one or more linear elements approximate a behavior of the nonlinear element while the wordline is inactive. A computer accessible storage medium storing a simulator that implements the method is contemplated, and the simulator itself is also contemplated, in various embodiments.

摘要翻译： 在一个实施例中，一种方法包括为存储器中的一列位单元创建仿真模型，模拟仿真模型以产生结果; 并显示用户的结果。 列中的每个位单元耦合到不同的字线，并且仿真模型包括一个或多个线性元件，代替耦合到非活动字线的每个位单元中的非线性元件。 一个或多个线性元素近似非线性元素的行为，而字线是无效的。 考虑了存储实现该方法的模拟器的计算机可访问存储介质，并且在各种实施例中也可以设想模拟器本身。

公开(公告)号：US20060112359A1

公开(公告)日：2006-05-25

申请号：US10994858

申请日：2004-11-22

申请人： Murat Becer ,  Ilan Algor ,  Amir Grinshpon ,  Rafi Levy ,  Chanhee Oh ,  Rajendran Panda ,  Vladimir Zolotov

发明人： Murat Becer ,  Ilan Algor ,  Amir Grinshpon ,  Rafi Levy ,  Chanhee Oh ,  Rajendran Panda ,  Vladimir Zolotov

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5031 ,  G06F17/5036

摘要： Processes and systems (300) for reducing pessimism in cross talk noise aware static timing analysis and thus resulting false path failures use either or both of effective delta delay noise (307) and path based delay noise (311) analysis. Effective delta delay determines an impact (312, 314, 316) on victim timing of an action by aggressors that occur during a region (209, 319, 321) where victim and aggressor timing windows overlap and determines an effective delta delay 317 corresponding to any portion 316 of the impact on victim timing that extends beyond the victim timing window. The effective delta delay is used to adjust the victim timing window. Path based delta delay determines an uncertainty (627, 637) in a switching time corresponding to a particular path for a victim resulting from an action (switching) by aggressors that occurs at the switching time 607, 613, i.e. during a switching time window (a2 to a2+u1) (613, 625) when uncertainty is included.

摘要翻译： 用于减少串扰噪声感知静态时序分析和因此导致的错误路径故障的悲观情况的过程和系统（300）使用有效的Δ延迟噪声（307）和基于路径的延迟噪声（311）分析中的一个或两者。 有效的延迟时间决定了在受害者和侵略者定时窗口重叠的区域（209,319,321）内发生的攻击者的动作的受害者定时的影响（312,314,316），并且确定对应于任何 部分316对受害者时机的影响超出受害者定时窗口。 有效的延迟时间用于调整受害者计时窗口。 基于路径的增量延迟确定在对应于由切换时间607,613上发生的攻击者的动作（切换）引起的受害者的特定路径的切换时间内的不确定性（627,637），即在切换时间窗口（ a 2到a 2 + u1）（613,625）。

公开(公告)号：US07251797B2

公开(公告)日：2007-07-31

申请号：US10994858

申请日：2004-11-22

申请人： Murat R. Becer ,  Ilan Algor ,  Amir Grinshpon ,  Rafi Levy ,  Chanhee Oh ,  Rajendran V. Panda ,  Vladimir P. Zolotov

发明人： Murat R. Becer ,  Ilan Algor ,  Amir Grinshpon ,  Rafi Levy ,  Chanhee Oh ,  Rajendran V. Panda ,  Vladimir P. Zolotov

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F17/5036

摘要： Processes and systems (300) for reducing pessimism in cross talk noise aware static timing analysis and thus resulting false path failures use either or both of effective delta delay noise (307) and path based delay noise (311) analysis. Effective delta delay determines an impact (312, 314, 316) on victim timing of an action by aggressors that occur during a region (209, 319, 321) where victim and aggressor timing windows overlap and determines an effective delta delay 317 corresponding to any portion 316 of the impact on victim timing that extends beyond the victim timing window. The effective delta delay is used to adjust the victim timing window. Path based delta delay determines an uncertainty (627, 637) in a switching time corresponding to a particular path for a victim resulting from an action (switching) by aggressors that occurs at the switching time 607, 613, i.e. during a switching time window (a2 to a2+u1) (613, 625) when uncertainty is included.

摘要翻译： 用于减少串扰噪声感知静态时序分析和因此导致的错误路径故障的悲观情况的过程和系统（300）使用有效的Δ延迟噪声（307）和基于路径的延迟噪声（311）分析中的一个或两者。 有效的延迟时间决定了在受害者和侵略者定时窗口重叠的区域（209,319,321）内发生的攻击者的动作的受害者定时的影响（312,314,316），并且确定对应于任何 部分316对受害者时机的影响超出受害者定时窗口。 有效的延迟时间用于调整受害者计时窗口。 基于路径的增量延迟确定在对应于由切换时间607,613上发生的攻击者的动作（切换）引起的受害者的特定路径的切换时间内的不确定性（627,637），即在切换时间窗口（ a 2到a 2 + u 1）（613,625）。

公开(公告)号：US07149674B1

公开(公告)日：2006-12-12

申请号：US09580854

申请日：2000-05-30

申请人： Supamas Sirichotiyakul ,  David T. Blaauw ,  Timothy J. Edwards ,  Chanhee Oh ,  Rajendran V. Panda ,  Judah L. Adelman ,  David Moshe ,  Abhijit Dharchoudhury

发明人： Supamas Sirichotiyakul ,  David T. Blaauw ,  Timothy J. Edwards ,  Chanhee Oh ,  Rajendran V. Panda ,  Judah L. Adelman ,  David Moshe ,  Abhijit Dharchoudhury

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F17/5022

摘要： A method of improving performance of a dual Vt integrated circuit is disclosed in which a first value is calculated for each transistor of the integrated circuit that has a first threshold voltage level. The first value is based at least in part on delay and leakage of the circuit calculated as if the corresponding transistor had a second threshold voltage level. One transistor is then selected based on the first values. The threshold voltage of the selected transistor is then set to the second threshold voltage level. The area of at least one transistor within the circuit is modified, and the circuit is then sized to a predetermined area. The process may then be repeated if the circuit performance fails to meet a defined constraint. In one embodiment, the performance determination includes calculating the leakage current of a set of DC-connected components into which the circuit is partitioned, determining dominant logic states for each of the components, estimating the leakage of each of these dominant logic states, and summing the weighted averages of these dominant components based on state probabilities.

摘要翻译： 公开了一种提高双电位集成电路性能的方法，其中针对具有第一阈值电压电平的集成电路的每个晶体管计算第一值。 第一个值至少部分地基于如同对应的晶体管具有第二阈值电压电平那样计算的延迟和泄漏。 然后基于第一值选择一个晶体管。 然后将所选择的晶体管的阈值电压设置为第二阈值电压电平。 电路内的至少一个晶体管的面积被修改，然后将电路的尺寸设定到预定区域。 如果电路性能不能满足规定的约束，则可以重复该过程。 在一个实施例中，性能确定包括计算电路被分配到其中的一组DC连接组件的漏电流，确定每个组件的主要逻辑状态，估计这些主要逻辑状态中的每一个的泄漏，以及求和 基于状态概率的这些主成分的加权平均值。

公开(公告)号：US06799153B1

公开(公告)日：2004-09-28

申请号：US09553271

申请日：2000-04-20

申请人： Supamas Sirichotiyakul ,  David T. Blaauw ,  Chanhee Oh ,  Vladimir P. Zolotov ,  Rafi Levy

发明人： Supamas Sirichotiyakul ,  David T. Blaauw ,  Chanhee Oh ,  Vladimir P. Zolotov ,  Rafi Levy

IPC分类号： G06F1750

CPC分类号： G06F17/5036 ,  G06F17/5031

摘要： A solution to perform cross coupling delay characterization for integrated circuits and other microprocessor applications. The invention properly models the integrated circuit in various configurations at various times to accommodate the non-linearities associated with driver circuitry and the undesirable capacitive coupling between nets within the integrated circuit, specifically those that are located within close proximity to one another and that generate deleterious effects of the transitions of the drivers from low to high, and from high to low. The invention provides for a computationally efficient solution to perform the delay characterization of the speeding up and slowing down of individual transition operations within the microprocessor. Accurate delay characterization provides for design engineers an accurate description of the worst case and best case scenarios of the integrated circuit or microprocessor that is needed for various applications such as the integration of the integrated circuit and microprocessor into a larger system.

摘要翻译： 对集成电路和其他微处理器应用执行交叉耦合延迟特性的解决方案。 本发明在各种时间适当地对各种配置的集成电路建模，以适应与驱动器电路相关联的非线性以及集成电路内的网络之间的不期望的电容耦合，特别是那些位于彼此非常接近并且产生有害的 司机过渡的影响从低到高，从高到低。 本发明提供了一种计算上有效的解决方案来执行微处理器内各个转换操作的加速和减慢的延迟表征。 精确的延迟表征为设计工程师提供了对于各种应用所需的集成电路或微处理器的最坏情况和最佳情况的精确描述，例如将集成电路和微处理器集成到更大的系统中。