发明授权
US08281170B1 System-on-chip power reduction through dynamic clock frequency 有权
通过动态时钟频率进行片上功耗降低

System-on-chip power reduction through dynamic clock frequency
摘要:
A dynamic clock frequency module includes a request evaluation module configured to generate a sum of requests to utilize a system bus from a plurality of modules. A frequency assignment module is configured to calculate a clock frequency for the system bus in response to the requests and adjust the clock frequency between at least two non-zero frequency values. A pulse stretch module is configured to increase a period of time that at least one of the requests is asserted in response to the sum.
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