Invention Grant
US08288224B2 Method for manufacturing capacitor lower electrodes of semiconductor memory
有权
制造半导体存储器的电容器下电极的方法
- Patent Title: Method for manufacturing capacitor lower electrodes of semiconductor memory
- Patent Title (中): 制造半导体存储器的电容器下电极的方法
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Application No.: US12699399Application Date: 2010-02-03
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Publication No.: US08288224B2Publication Date: 2012-10-16
- Inventor: Shin-Bin Huang , Tzung-Han Lee , Chung-Lin Huang
- Applicant: Shin-Bin Huang , Tzung-Han Lee , Chung-Lin Huang
- Applicant Address: TW Taoyuan County
- Assignee: Inotera Memories, Inc.
- Current Assignee: Inotera Memories, Inc.
- Current Assignee Address: TW Taoyuan County
- Agency: Rosenberg, Klein & Lee
- Priority: TW98135584A 20091021
- Main IPC: H01L21/8242
- IPC: H01L21/8242

Abstract:
A method for manufacturing capacitor lower electrodes includes a dielectric layer, a first silicon nitride layer and a hard mask layer; partially etching the hard mask layer, the first silicon nitride layer and the dielectric layer to form a plurality of concave portions; depositing a second silicon nitride layer onto the hard mask layer and into the concave portions; partially etching the second silicon nitride layer, the hard mask layer and the dielectric layer to form a plurality of trenches; forming a capacitor lower electrode within each trench and partially etching the first silicon nitride layer, the second silicon nitride layer, the dielectric layer and the capacitor lower electrodes to form an etching area; and etching and removing the dielectric layer from the etching area, thereby a periphery of each capacitor lower electrode is surrounded and attached to by the second silicon nitride layer.
Public/Granted literature
- US20110092044A1 METHOD FOR MANUFACTURING CAPACITOR LOWER ELECTRODES OF SEMICONDUCTOR MEMORY Public/Granted day:2011-04-21
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