公开(公告)号：US09479009B2

公开(公告)日：2016-10-25

申请号：US13234625

申请日：2011-09-16

申请人： Tzung-Han Lee ,  Tsung-Te Lee

发明人： Tzung-Han Lee ,  Tsung-Te Lee

IPC分类号： H02J4/00 ,  H02J9/06

CPC分类号： H02J9/06 ,  Y10T307/305 ,  Y10T307/50

摘要： A power system for actively maintaining operation includes a power supply unit electrically connected to a commercial power source, a back panel electrically connected to the power supply unit and an ON/OFF control unit. The power supply unit has an OFF state and an operating state to convert the power provided by the commercial power source for outputting. The back panel converges the output of the power supply unit and provides a driving power. The ON/OFF control unit has an input detection terminal electrically connected to the commercial power source to detect whether the commercial power source supplies power and at least one operation signal terminal to output an operation signal upon judging that the commercial power source supplies power to drive the power supply unit to enter the operating state.

摘要翻译： 用于主动维护操作的电力系统包括电连接到商用电源的电源单元，电连接到电源单元的后面板和ON / OFF控制单元。 电源单元具有OFF状态和用于转换由商用电源提供的电力进行输出的操作状态。 后面板会收敛电源单元的输出并提供驱动电源。 ON / OFF控制单元具有电连接到商用电源的输入检测端子，用于检测商用电源是否提供电力，以及至少一个操作信号端子，以在判断商用电源供电以驱动时输出操作信号 电源单元进入运行状态。

公开(公告)号：US08873280B2

公开(公告)日：2014-10-28

申请号：US13282771

申请日：2011-10-27

申请人： Tzung Han Lee ,  Chung-Lin Huang ,  Ron Fu Chu

发明人： Tzung Han Lee ,  Chung-Lin Huang ,  Ron Fu Chu

IPC分类号： G11C11/00

CPC分类号： H01L27/228 ,  G11C11/161 ,  G11C11/1659 ,  H01L43/08

摘要： A spin transfer torque random access memory includes a substance unit, a source line unit, an insulation unit, a transistor unit, a MTJ unit, and a bit line unit. The substance unit includes a substance layer. The source line unit includes a plurality of source lines formed inside the substance layer. The transistor unit includes a plurality of transistors respectively disposed on the source lines. Each transistor includes a source region formed on each corresponding source line, a drain region formed above the source region, a channel region formed between the source region and the drain region, and a surrounding gate region surrounding the source region, the drain region, and the channel region. The MTJ unit includes a plurality of MTJ structures respectively disposed on the transistors. The bit line unit includes at least one bit line disposed on the MTJ unit.

摘要翻译： 自旋传递转矩随机存取存储器包括物质单元，源极线单元，绝缘单元，晶体管单元，MTJ单元和位线单元。 物质单元包括物质层。 源极线单元包括形成在物质层内部的多个源极线。 晶体管单元包括分别设置在源极线上的多个晶体管。 每个晶体管包括形成在每个对应源极线上的源极区域，形成在源极区域上方的漏极区域，形成在源极区域和漏极区域之间的沟道区域，以及围绕源极区域，漏极区域和 通道区域。 MTJ单元包括分别设置在晶体管上的多个MTJ结构。 位线单元包括设置在MTJ单元上的至少一个位线。

公开(公告)号：US08703575B2

公开(公告)日：2014-04-22

申请号：US13421996

申请日：2012-03-16

申请人： Tzung-Han Lee ,  Chung-Lin Huang ,  Ron Fu Chu

发明人： Tzung-Han Lee ,  Chung-Lin Huang ,  Ron Fu Chu

IPC分类号： H01L21/76 ,  H01L21/00

CPC分类号： H01L21/76224

摘要： The instant disclosure relates to a method of forming an isolation area. The method includes the steps of: providing a substrate having a first type of ion dopants, where the substrate has a plurality of trenches formed on the cell areas and the isolation area between the cell areas of the substrate, with the side walls of the trenches having an oxidation layer formed thereon and the trenches are filled with a metallic structure; removing the metallic structure from the trenches of the isolation area; implanting a second type of ions into the substrate under the trenches of the isolation area; and filling all the trenches with an insulating structure, where the trenches of the isolation area are filled up fully by the insulating structure to form a non-metallic isolation area.

摘要翻译： 本公开涉及形成隔离区域的方法。 该方法包括以下步骤：提供具有第一类型的离子掺杂剂的衬底，其中衬底具有形成在单元区域上的多个沟槽和衬底的单元区域之间的隔离区域与沟槽的侧壁 其上形成有氧化层，并且沟槽填充有金属结构; 从隔离区的沟槽移除金属结构; 在隔离区的沟槽下方将第二类型的离子注入到衬底中; 并用绝缘结构填充所有沟槽，其中隔离区域的沟槽由绝缘结构完全填充以形成非金属隔离区域。

公开(公告)号：US08486801B2

公开(公告)日：2013-07-16

申请号：US13297276

申请日：2011-11-16

申请人： Tzung-Han Lee ,  Chung-Lin Huang ,  Ron Fu Chu

发明人： Tzung-Han Lee ,  Chung-Lin Huang ,  Ron Fu Chu

IPC分类号： H01L21/00 ,  H01L27/108 ,  H01L29/94

CPC分类号： H01L27/10894 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10888 ,  H01L29/66545

摘要： A fabricating method of a DRAM structure includes providing a substrate comprising a memory array region and a peripheral region. A buried gate transistor is disposed within the memory array region, and a planar gate transistor is disposed within the peripheral region. Furthermore, an interlayer dielectric layer covers the memory array region, the buried gate transistor and the planar gate transistor. Then, a capping layer of the planar gate transistor and part of the interlayer dielectric layer are removed simultaneously so that a first contact hole, a second contact hole and a third contact hole are formed in the interlayer dielectric layer. A drain doping region of the buried gate transistor is exposed through the first contact hole, a doping region of the planar gate transistor is exposed through the second contact hole, and a gate electrode of the planar gate transistor is exposed through the third contact hole.

摘要翻译： DRAM结构的制造方法包括提供包括存储器阵列区域和外围区域的衬底。 掩埋栅极晶体管设置在存储器阵列区域内，并且平面栅极晶体管设置在周边区域内。 此外，层间电介质层覆盖存储器阵列区域，掩埋栅极晶体管和平面栅极晶体管。 然后，同时去除平面栅晶体管的覆盖层和层间电介质层的一部分，使得在层间电介质层中形成第一接触孔，第二接触孔和第三接触孔。 埋入栅极晶体管的漏极掺杂区域通过第一接触孔露出，平面栅极晶体管的掺杂区域通过第二接触孔露出，平面栅极晶体管的栅电极通过第三接触孔露出。

公开(公告)号：US08471664B1

公开(公告)日：2013-06-25

申请号：US13454805

申请日：2012-04-24

申请人： Yung-Hsin Huang ,  Tzung-Han Lee ,  Yun-Chen Chen

发明人： Yung-Hsin Huang ,  Tzung-Han Lee ,  Yun-Chen Chen

IPC分类号： H01F27/30 ,  H01F27/28

CPC分类号： H01F27/2866 ,  H01F27/306 ,  H01F2027/065 ,  H01F2027/2814

摘要： A transformer without coil racks includes a winding set, multiple conductive plates and an insulation mounting sheet. The winding set includes a coil portion and a magnetic core set running through the coil portion. The magnetic core set includes at least one inner magnetic core portion and at least two outer magnetic core portions that are spaced from each other by a gap. Each conductive plate includes a connecting section and two extended arms connected to two ends of the connecting section and running through the gap. The insulation mounting sheet includes multiple retaining slots corresponding to the gap to allow the extended arms to pass through and multiple retaining portions each being formed between two neighboring retaining slots to prevent the extended arms from contacting each other. The conductive plates run through the retaining slots and are confined by the retaining portions from moving.

摘要翻译： 没有线圈架的变压器包括绕组，多个导电板和绝缘安装片。 线圈组包括线圈部分和贯穿线圈部分的磁芯组。 磁芯组包括至少一个内部磁芯部分和至少两个彼此间隔开的外部磁芯部分。 每个导电板包括连接部分和连接到连接部分两端并延伸通过间隙的两个延伸臂。 绝缘安装片包括对应于间隙的多个保持槽，以允许延伸的臂通过，并且每个保持部分形成在两个相邻的保持槽之间，以防止伸出的臂彼此接触。 导电板穿过保持槽并被保持部分限制移动。

公开(公告)号：US08471320B2

公开(公告)日：2013-06-25

申请号：US13343668

申请日：2012-01-04

申请人： Tzung-Han Lee ,  Chung-Lin Huang ,  Ron Fu Chu

发明人： Tzung-Han Lee ,  Chung-Lin Huang ,  Ron Fu Chu

IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L27/10823 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10891 ,  H01L28/90

摘要： A memory array layout includes an active region array having a plurality of active regions, wherein the active regions are arranged alternatively along a second direction and parts of the side of the adjacent active regions are overlapped along a second direction; a plurality of first doped region, wherein each first doped region is disposed in a middle region; a plurality of second doped region, wherein each second doped region is disposed in a distal end region respectively; a plurality of recessed gate structures; a plurality of word lines electrically connected to each recessed gate structure respectively; a plurality of digit lines electrically connected to the first doped region respectively; and a plurality of capacitors electrically connected to each second doped region respectively.

摘要翻译： 存储器阵列布局包括具有多个有源区域的有源区域阵列，其中有源区域沿着第二方向交替布置，并且相邻有源区域的一部分侧沿第二方向重叠; 多个第一掺杂区域，其中每个第一掺杂区域设置在中间区域中; 多个第二掺杂区域，其中每个第二掺杂区域分别设置在远端区域中; 多个凹入栅结构; 分别电连接到每个凹入栅结构的多个字线; 分别电连接到第一掺杂区的多个数字线; 以及分别与每个第二掺杂区域电连接的多个电容器。

公开(公告)号：US20130062676A1

公开(公告)日：2013-03-14

申请号：US13239364

申请日：2011-09-21

申请人： Tzung-Han Lee ,  Chung-Lin Huang ,  Ron Fu Chu ,  Dah-Wei Liu

发明人： Tzung-Han Lee ,  Chung-Lin Huang ,  Ron Fu Chu ,  Dah-Wei Liu

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  H01L29/40114

摘要： A flash memory structure includes a semiconductor substrate, a gate dielectric layer on the semiconductor substrate, a floating gate on the gate dielectric layer, a capacitor dielectric layer conformally covering the floating gate, wherein the capacitor dielectric layer forms a top surface and four sidewall surfaces; and an isolated conductive cap layer covering the top surface and the four sidewall surfaces.

摘要翻译： 闪速存储器结构包括半导体衬底，半导体衬底上的栅极电介质层，栅极介电层上的浮置栅极，保形地覆盖浮置栅极的电容器电介质层，其中电容器介电层形成顶表面和四个侧壁表面 ; 以及覆盖顶表面和四个侧壁表面的隔离的导电盖层。

公开(公告)号：US08373220B1

公开(公告)日：2013-02-12

申请号：US13224561

申请日：2011-09-02

申请人： Tzung Han Lee ,  Chung-Lin Huang ,  Ron Fu Chu

发明人： Tzung Han Lee ,  Chung-Lin Huang ,  Ron Fu Chu

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  H01L29/42328 ,  H01L29/7887

摘要： A NAND type flash memory for increasing data read/write reliability includes a semiconductor substrate unit, a base unit, and a plurality of data storage units. The semiconductor substrate unit includes a semiconductor substrate. The base unit includes a first dielectric layer formed on the semiconductor substrate. The data storage units are formed on the first dielectric layer. Each data storage unit includes two floating gates formed on the first dielectric layer, two inter-gate dielectric layers respectively formed on the two floating gates, two control gates respectively formed on the two inter-gate dielectric layers, a second dielectric layer formed on the first dielectric layer, between the two floating gates, between the two inter-gate dielectric layers, and between the two control gates, and a third dielectric layer formed on the first dielectric layer and surrounding and connecting with the two floating gates, the two inter-gate dielectric layers, and the two control gates.

摘要翻译： 用于增加数据读/写可靠性的NAND型闪速存储器包括半导体衬底单元，基本单元和多个数据存储单元。 半导体衬底单元包括半导体衬底。 基座单元包括形成在半导体衬底上的第一电介质层。 数据存储单元形成在第一电介质层上。 每个数据存储单元包括形成在第一介电层上的两个浮置栅极，分别形成在两个浮置栅极上的两个栅极间电介质层，分别形成在两个栅极间电介质层上的两个控制栅极， 第一电介质层，两个浮置栅极之间，两个栅极间电介质层之间以及两个控制栅极之间，以及形成在第一介电层上并围绕并连接两个浮动栅极的第三介质层， - 门电介质层和两个控制门。

公开(公告)号：US08283709B2

公开(公告)日：2012-10-09

申请号：US12899721

申请日：2010-10-07

申请人： Tzung Han Lee ,  Chung-Lin Huang ,  Hsien-Wen Liu

发明人： Tzung Han Lee ,  Chung-Lin Huang ,  Hsien-Wen Liu

IPC分类号： H01L29/772

CPC分类号： H01L21/76224 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66621 ,  H01L29/78

摘要： A semiconductor device is disclosed which includes a silicide substrate, a nitride layer, two STIs, and a strain nitride. The silicide substrate has two doping areas. The nitride layer is deposited on the silicide substrate. The silicide substrate and the nitride layer have a recess running through. The two doping areas are at two sides of the recess. The end of the recess has an etching space bigger than the recess. The top of the silicide substrate has a fin-shaped structure. The two STIs are at the two opposite sides of the silicide substrate (recess). The strain nitride is spacer-formed in the recess and attached to the side wall of the silicide substrate, nitride layer, two STIs. The two doping areas cover the strain nitride. As a result, the efficiency of semiconductor is improved, and the drive current is increased.

摘要翻译： 公开了一种半导体器件，其包括硅化物衬底，氮化物层，两个STI和应变氮化物。 硅化物衬底具有两个掺杂区域。 氮化物层沉积在硅化物衬底上。 硅化物衬底和氮化物层具有贯穿的凹槽。 两个掺杂区位于凹槽的两侧。 凹部的端部具有比凹部大的蚀刻空间。 硅化物衬底的顶部具有鳍状结构。 两个STI位于硅化物衬底（凹槽）的两个相对侧。 应变氮化物在凹槽​​中间隔形成并附着到硅化物衬底，氮化物层，两个STI的侧壁上。 两个掺杂区域覆盖了应变氮化物。 结果，提高了半导体的效率，并且提高了驱动电流。

公开(公告)号：US07638390B2

公开(公告)日：2009-12-29

申请号：US11852185

申请日：2007-09-07

申请人： Tzung-Han Lee ,  Kuang-Pi Lee ,  Wen-Jeng Lin ,  Rern-Hurng Larn

发明人： Tzung-Han Lee ,  Kuang-Pi Lee ,  Wen-Jeng Lin ,  Rern-Hurng Larn

IPC分类号： H01L21/8242

CPC分类号： H01L27/1087 ,  H01L27/11 ,  Y10S257/903

摘要： A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an opening. The transistor is set up over the active region of the substrate. The source region of the transistor is next to the opening. The upper electrode is set up over the opening such that the opening is completely filled. The capacitor dielectric layer is set up between the upper electrode and the substrate.

摘要翻译： 至少包括衬底，晶体管，上电极和电容器电介质层的静态随机存取存储器（SRAM）单元结构。 在衬底中设置器件隔离结构以限定有源区。 活动区域有一个开口。 晶体管设置在衬底的有源区上。 晶体管的源极区域靠近开口。 将上电极设置在开口上方，使得开口完全充满。 电容器介电层设置在上电极和衬底之间。