发明授权
- 专利标题: Variable read latency on a serial memory bus
- 专利标题(中): 串行存储器总线上的可变读延迟
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申请号: US12729905申请日: 2010-03-23
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公开(公告)号: US08291126B2公开(公告)日: 2012-10-16
- 发明人: Clifford Alan Zitlaw
- 申请人: Clifford Alan Zitlaw
- 申请人地址: US CA Sunnyvale
- 专利权人: Spansion LLC
- 当前专利权人: Spansion LLC
- 当前专利权人地址: US CA Sunnyvale
- 代理机构: Frommer, Lawrence & Haug LLP
- 代理商 Matthew M. Gaffney
- 主分类号: G06F3/00
- IPC分类号: G06F3/00 ; G06F13/00
摘要:
One or more embodiments provide a method and system of reading data from a variable-latency memory, via a serial input/output memory data interface. The system includes a memory having a variable-latency access time, a memory controller, and a serial data bus coupling the memory controller to the memory. The memory controller communicates a Read command to the memory and forces the serial data bus low for a limited time. The memory then forces the bus low and the memory controller then releases the bus. When the memory is ready to provide data, the memory provides a high signal on the serial data bus.
公开/授权文献
- US20110238866A1 VARIABLE READ LATENCY ON A SERIAL MEMORY BUS 公开/授权日:2011-09-29
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