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公开(公告)号：US20110179215A1
公开(公告)日：2011-07-21
申请号：US12691633
申请日：2010-01-21
申请人： Clifford Alan Zitlaw , Anthony Le
发明人： Clifford Alan Zitlaw , Anthony Le
CPC分类号： G11C16/20 , G11C7/1072 , G11C7/20
摘要： The subject systems and/or methods relate to a high speed memory device that enables a preamble pattern to be updated after manufacture. A high speed memory device can include a FLASH module and a RAM module. The FLASH module can include an initial preamble pattern, wherein the initial preamble pattern is loaded during a power-up of the high speed memory. The RAM module can include a default preamble pattern, wherein the default preamble pattern is loaded after the power-up of the high speed memory. The initial preamble pattern or the default preamble pattern can be defined by a manufacture of the high speed memory or an OEM of the high speed memory. Additionally, the initial preamble pattern or the default preamble pattern can be updated with a customized preamble pattern based upon a target environment.
摘要翻译： 主题系统和/或方法涉及能够在制造之后更新前导码模式的高速存储器设备。 高速存储器件可以包括闪存模块和RAM模块。 FLASH模块可以包括初始前导码模式，其中在高速存储器的加电期间加载初始前导码模式。 RAM模块可以包括默认前导码模式，其中在高速存储器上电之后加载默认前导码模式。 可以通过制造高速存储器或高速存储器的OEM来定义初始前导码模式或默认前导码模式。 另外，可以使用基于目标环境的定制前导码模式来更新初始前导码模式或默认前导码模式。
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公开(公告)号：US08291126B2
公开(公告)日：2012-10-16
申请号：US12729905
申请日：2010-03-23
申请人： Clifford Alan Zitlaw
发明人： Clifford Alan Zitlaw
CPC分类号： G06F13/161 , G06F13/4291
摘要： One or more embodiments provide a method and system of reading data from a variable-latency memory, via a serial input/output memory data interface. The system includes a memory having a variable-latency access time, a memory controller, and a serial data bus coupling the memory controller to the memory. The memory controller communicates a Read command to the memory and forces the serial data bus low for a limited time. The memory then forces the bus low and the memory controller then releases the bus. When the memory is ready to provide data, the memory provides a high signal on the serial data bus.
摘要翻译： 一个或多个实施例提供了通过串行输入/输出存储器数据接口从可变延迟存储器读取数据的方法和系统。 该系统包括具有可变延迟访问时间的存储器，存储器控制器和将存储器控制器耦合到存储器的串行数据总线。 存储器控制器将Read命令传送到存储器，并在有限的时间内迫使串行数据总线为低电平。 然后存储器强制总线为低电平，然后存储器控制器释放总线。 当存储器准备好提供数据时，存储器在串行数据总线上提供高信号。
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公开(公告)号：US20120066433A1
公开(公告)日：2012-03-15
申请号：US12879992
申请日：2010-09-10
摘要： A memory device is provided. The memory device includes a preamble disable memory and a memory controller. The preamble disable memory is arranged to store preamble disable data. The preamble disable data includes an indication as to whether a read preamble should be enabled or disabled. In response to a read command, if the preamble disable data includes an indication that the read preamble should be enabled, the memory controller provides the read preamble. Alternatively, in response to the read command, if the preamble disable data includes an indication that the read preamble should be disabled, the memory controller disables the read preamble.
摘要翻译： 提供存储器件。 存储器件包括前导禁止存储器和存储器控制器。 前导码禁用存储器被设置为存储前导码禁用数据。 前导码禁用数据包括关于读前导码应当被启用还是禁用的指示。 响应于读取命令，如果前导码禁用数据包括应该启用读取前同步码的指示，则存储器控制器提供读取的前同步码。 或者，响应于读取命令，如果前导码禁用数据包括应该禁用读取前导码的指示，则存储器控制器禁用读取前同步码。
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公开(公告)号：US20120063243A1
公开(公告)日：2012-03-15
申请号：US12880018
申请日：2010-09-10
CPC分类号： G11C7/1093 , G11C29/022 , G11C29/028
摘要： A data capturing device is provided. The data capturing device includes a data capturing device controller and data capturing components. The data capturing device is arranged to send a burst read command. Each of the data capturing components includes a DLL component, a data sampling component, a comparison component, and a valid clock calculation component. The DLL component is arranged to provide clock signals. The data sampling component is arranged to receive a serial data signal that includes a read preamble, where the read preamble includes a training pattern, and to sample the serial data signal with each of the clock signals. The comparison component is arranged to compare each of the sampled data signals with an expected training pattern. The valid clock calculation component is arranged to, based on the comparisons, select one of the clock signals as the valid clock signal for locking the DLL component to.
摘要翻译： 提供数据采集装置。 数据采集装置包括数据采集装置控制器和数据采集部件。 数据捕获装置被配置为发送突发读取命令。 每个数据捕获组件包括DLL组件，数据采样组件，比较组件和有效时钟计算组件。 DLL组件被设置成提供时钟信号。 数据采样部件被布置为接收包括读取前置码的串行数据信号，其中读取前同步码包括训练模式，并且利用每个时钟信号对串行数据信号进行采样。 比较部件被布置为将每个采样数据信号与预期的训练模式进行比较。 有效时钟计算部件被配置为基于比较，选择一个时钟信号作为用于锁定DLL组件的有效时钟信号。
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公开(公告)号：US20110153915A1
公开(公告)日：2011-06-23
申请号：US12646279
申请日：2009-12-23
申请人： Clifford Alan Zitlaw
发明人： Clifford Alan Zitlaw
CPC分类号： G11C16/32 , G11C16/26 , G11C2216/30
摘要： Systems and/or methods are provided that facilitate data capture optimization for devices accessing memories via a bus. In an aspect, a memory can output a read preamble prior to pushing data onto a bus. The read preamble can be a known sequence of one or more bits. A host device accessing the memory via the bus can analyze the read preamble and, particularly, timing characteristics of the read preamble. The timing characteristics can be utilized to identify an optimal capture point within a window of data validity.
摘要翻译： 提供了用于经由总线访问存储器的设备的数据捕获优化的系统和/或方法。 在一方面，存储器可以在将数据推送到总线之前输出读取前同步码。 读取的前同步码可以是一个或多个比特的已知序列。 通过总线访问存储器的主机设备可以分析读取前置码，特别是读取前置码的定时特性。 时序特征可用于识别数据有效性窗口内的最佳捕获点。
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6.发明授权Apparatus, method, and manufacture for using a read preamble to optimize data capture 有权用于使用读取前导码优化数据捕获的装置，方法和制造公开(公告)号：US09355051B2
公开(公告)日：2016-05-31
申请号：US12880021
申请日：2010-09-10
申请人： Clifford Alan Zitlaw
发明人： Clifford Alan Zitlaw
CPC分类号： G06F13/28 , G11C7/22 , H04L27/2692
摘要： A memory controller is provided. In response to a burst read command that includes a target address, the memory controller provides, to one or more busses, data stored in memory at the target address after dummy clock cycles have occurred. The memory controller also provides a preamble on the bus(ses) during some of the dummy clock cycles. The preamble includes a data training pattern.
摘要翻译： 提供存储器控制器。 响应于包括目标地址的突发读取命令，存储器控制器在发生虚拟时钟周期之后向一个或多个总线提供存储在目标地址的存储器中的数据。 存储器控制器还在一些虚拟时钟周期期间在总线上提供前置码（ses）。 前导码包括数据训练模式。
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公开(公告)号：US08990605B2
公开(公告)日：2015-03-24
申请号：US12879992
申请日：2010-09-10
摘要： A memory device is provided. The memory device includes a preamble disable memory and a memory controller. The preamble disable memory is arranged to store preamble disable data. The preamble disable data includes an indication as to whether a read preamble should be enabled or disabled. In response to a read command, if the preamble disable data includes an indication that the read preamble should be enabled, the memory controller provides the read preamble. Alternatively, in response to the read command, if the preamble disable data includes an indication that the read preamble should be disabled, the memory controller disables the read preamble.
摘要翻译： 提供存储器件。 存储器件包括前导禁止存储器和存储器控制器。 前导码禁用存储器被设置为存储前导码禁用数据。 前导码禁用数据包括关于读前导码应当被启用还是禁用的指示。 响应于读取命令，如果前导码禁用数据包括应该启用读取前同步码的指示，则存储器控制器提供读取的前同步码。 或者，响应于读取命令，如果前导码禁用数据包括应该禁用读取前导码的指示，则存储器控制器禁用读取前同步码。
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公开(公告)号：US20130191558A1
公开(公告)日：2013-07-25
申请号：US13357842
申请日：2012-01-25
申请人： Clifford Alan Zitlaw
发明人： Clifford Alan Zitlaw
IPC分类号： G06F3/00
CPC分类号： G06F9/44 , G06F13/38 , G06F13/4243 , G11C7/222 , G11C2207/2272
摘要： A memory device includes a memory array, an output buffer, an initial latency register, and an output signal. Often times a host device that interfaces with the memory device is clocked at high rate such that data extraction rates of the memory device are not adequate to support a gapless data transfer. The output signal is operable to stall a transmission between the memory device and the host device when data extraction rates from the memory array are not adequate to support output rates of the output buffer.
摘要翻译： 存储器件包括存储器阵列，输出缓冲器，初始延迟寄存器和输出信号。 通常，与存储器件连接的主机设备以高速率被计时，使得存储器件的数据提取速率不足以支持无间隙数据传输。 当来自存储器阵列的数据提取速率不足以支持输出缓冲器的输出速率时，输出信号可操作以阻止存储器件和主机器件之间的传输。
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公开(公告)号：US08140778B1
公开(公告)日：2012-03-20
申请号：US12880018
申请日：2010-09-10
CPC分类号： G11C7/1093 , G11C29/022 , G11C29/028
摘要： A data capturing device is provided. The data capturing device includes a data capturing device controller and data capturing components. The data capturing device is arranged to send a burst read command. Each of the data capturing components includes a DLL component, a data sampling component, a comparison component, and a valid clock calculation component. The DLL component is arranged to provide clock signals. The data sampling component is arranged to receive a serial data signal that includes a read preamble, where the read preamble includes a training pattern, and to sample the serial data signal with each of the clock signals. The comparison component is arranged to compare each of the sampled data signals with an expected training pattern. The valid clock calculation component is arranged to, based on the comparisons, select one of the clock signals as the valid clock signal for locking the DLL component to.
摘要翻译： 提供数据采集装置。 数据采集装置包括数据采集装置控制器和数据采集部件。 数据捕获装置被配置为发送突发读取命令。 每个数据捕获组件包括DLL组件，数据采样组件，比较组件和有效时钟计算组件。 DLL组件被设置成提供时钟信号。 数据采样部件被布置为接收包括读取前置码的串行数据信号，其中读取前同步码包括训练模式，并且利用每个时钟信号对串行数据信号进行采样。 比较部件被布置为将每个采样数据信号与预期的训练模式进行比较。 有效时钟计算部件被配置为基于比较，选择一个时钟信号作为用于锁定DLL组件的有效时钟信号。
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10.发明授权公开(公告)号：US09223726B2
公开(公告)日：2015-12-29
申请号：US12879936
申请日：2010-09-10
申请人： Clifford Alan Zitlaw , Anthony Le
发明人： Clifford Alan Zitlaw , Anthony Le
CPC分类号： G06F12/16 , G06F1/12 , G06F11/10 , G08B5/222 , G11C5/066 , G11C7/1006 , G11C7/222 , G11C11/5621 , G11C16/00 , H04L7/04
摘要： A memory device is provided. The memory device includes a preamble memory and a memory controller. The preamble memory is arranged to store a read preamble such that the read preamble includes a training pattern that is suitable for aligning a capture point for read data. Further, the training pattern is programmable such that the training pattern can be altered at least once subsequent to manufacture of the preamble memory. In response to a read command, the memory controller provides the read preamble stored in the preamble memory, as well as the read data.
摘要翻译： 提供存储器件。 该存储器件包括前置码存储器和存储器控制器。 前导码存储器被布置为存储读取前导码，使得读取前导码包括适合于对准用于读取数据的捕获点的训练模式。 此外，训练模式是可编程的，使得训练模式可以在制造前同步码存储器之后至少改变一次。 响应于读取命令，存储器控制器提供存储在前导码存储器中的读取前导码以及读取的数据。
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