发明授权
US08300452B2 Structure and method for improving storage latch susceptibility to single event upsets
有权
用于改善单个事件扰乱的存储锁存敏感性的结构和方法
- 专利标题: Structure and method for improving storage latch susceptibility to single event upsets
- 专利标题(中): 用于改善单个事件扰乱的存储锁存敏感性的结构和方法
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申请号: US13050052申请日: 2011-03-17
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公开(公告)号: US08300452B2公开(公告)日: 2012-10-30
- 发明人: Ethan H. Cannon , Toshiharu Furukawa , David Horak , Charles W. Koburger, III , Jack A. Mandelman
- 申请人: Ethan H. Cannon , Toshiharu Furukawa , David Horak , Charles W. Koburger, III , Jack A. Mandelman
- 申请人地址: US NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: US NY Armonk
- 代理机构: Cantor Colburn LLP
- 代理商 Michael LeStrange
- 主分类号: G11C11/00
- IPC分类号: G11C11/00
摘要:
A digital logic storage structure includes cross coupled first and second complementary metal oxide semiconductor (CMOS) inverters formed on a semiconductor substrate, the CMOS inverters including a first storage node and a second storage node that is the logical complement of the first storage node; both of the first and second storage nodes each selectively coupled to a deep trench capacitor through a switching transistor, with the switching transistors controlled by a common capacitance switch line coupled to gate conductors thereof; wherein, in a first mode of operation, the switching transistors are rendered nonconductive so as to isolate the deep trench capacitors from the inverter storage nodes and, in a second mode of operation, the switching transistors are rendered conductive so as to couple the deep trench capacitors to their respective storage nodes, thereby providing increased resistance of the storage nodes to single event upsets (SEUs).