A phase change memory device includes a memory cell array having a plurality of phase change memory cells, a read bias generating circuit, a clamping circuit and a clamping control signal generating circuit (CCSGC). The read bias generating circuit provides a sensing node with a read bias for reading a resistance level of a selected phase change memory cell. The clamping circuit controls an amount of clamping current flowing into a bit line connected with the selected phase change memory cell. The CCSGC provides the clamping control signal to the clamping circuit and adjusts a level of the clamping control signal.