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1.发明申请NONVOLATILE MEMORY DEVICE, STORAGE DEVICE HAVING THE SAME, AND OPERATION METHOD THEREOF 有权非易失存储器件，具有该存储器件的存储器件及其操作方法公开(公告)号：US20160260489A1
公开(公告)日：2016-09-08
申请号：US15003113
申请日：2016-01-21
Applicant: CHEON AN LEE , MU-HUI PARK , JIHO CHO , JI-YOUNG LEE , YOON-HEE CHOI
Inventor： CHEON AN LEE , MU-HUI PARK , JIHO CHO , JI-YOUNG LEE , YOON-HEE CHOI
CPC classification number: G11C16/16 , G11C16/08 , G11C16/10 , G11C16/26 , G11C16/3427
Abstract: A method of operating a nonvolatile memory device is provided as follows. The nonvolatile memory device includes memory blocks each of which has word lines. A setup voltage is applied to the word lines. A word line voltage is applied to a first word line selected from the word lines. Recovery voltages are applied to the word lines. Each recovery voltage is applied to at least one corresponding word line of the word lines. The recovery voltages have different voltage levels from each other.
Abstract translation: 如下提供操作非易失性存储器件的方法。 非易失性存储器件包括每个都具有字线的存储器块。 设置电压被施加到字线。 字线电压被施加到从字线选择的第一字线。 恢复电压被施加到字线。 每个恢复电压被施加到字线的至少一个对应的字线。 恢复电压彼此具有不同的电压电平。
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公开(公告)号：US20110188303A1
公开(公告)日：2011-08-04
申请号：US13064672
申请日：2011-04-07
Applicant: Beak-Hyung Cho , Woo-Yeong Cho , Mu-Hui Park
Inventor： Beak-Hyung Cho , Woo-Yeong Cho , Mu-Hui Park
IPC: G11C11/00
CPC classification number: G11C13/0069 , G11C13/0004 , G11C2013/0078 , G11C2013/0092 , G11C2213/72
Abstract: A phase change memory device may include a memory cell array, a write driver, and/or a control unit. The memory cell array may include a plurality of memory cells. The write driver may be configured to provide a program current to the memory cell array for setting a state of a phase change material to program a selected memory cell. The write driver may be configured to provide the program current such that the program current has a plurality of steps. The control unit may be configured to receive step information for adjusting a magnitude and a width of each step of the program current during a test operation and provide the step information to the write driver during a normal operation.
Abstract translation: 相变存储器件可以包括存储单元阵列，写入驱动器和/或控制单元。 存储单元阵列可以包括多个存储单元。 写入驱动器可以被配置为向存储器单元阵列提供程序电流，用于设置相变材料的状态以对选定的存储单元进行编程。 写驱动器可以被配置为提供程序电流，使得程序电流具有多个步骤。 控制单元可以被配置为在测试操作期间接收用于调整程序电流的每个步骤的幅度和宽度的步骤信息，并且在正常操作期间将该步骤信息提供给写入驱动器。
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公开(公告)号：US07986551B2
公开(公告)日：2011-07-26
申请号：US12690999
申请日：2010-01-21
Applicant: Mu-hui Park , Beak-hyung Cho , Hyung-rok Oh
Inventor： Mu-hui Park , Beak-hyung Cho , Hyung-rok Oh
IPC: G11C11/00
CPC classification number: G11C13/0064 , G11C13/0004 , G11C13/0038 , G11C13/0069 , G11C2013/0078 , G11C2013/0092
Abstract: In a phase-change random access memory (PRAM) device, a write operation is performed by applying a set pulse to failed PRAM cells. The set pulse comprises a plurality of stages sequentially decreasing from a first current magnitude to a second current magnitude. The first current magnitude or the second current magnitude varies from one write loop to another.
Abstract translation: 在相变随机存取存储器（PRAM）装置中，通过将设置的脉冲施加到失败的PRAM单元来执行写入操作。 设置脉冲包括从第一电流幅度顺序地减小到第二电流幅度的多个级。 第一电流幅度或第二电流幅度从一个写入环路变化到另一个写入环路。
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4.发明授权公开(公告)号：US07936612B2
公开(公告)日：2011-05-03
申请号：US12654338
申请日：2009-12-17
Applicant: Beak-Hyung Cho , Woo-Yeong Cho , Mu-Hui Park
Inventor： Beak-Hyung Cho , Woo-Yeong Cho , Mu-Hui Park
IPC: G11C7/10
CPC classification number: G11C13/0069 , G11C13/0004 , G11C2013/0078 , G11C2013/0092 , G11C2213/72
Abstract: A phase change memory device may include a memory cell array, a write driver, and/or a control unit. The memory cell array may include a plurality of memory cells. The write driver may be configured to provide a program current to the memory cell array for setting a state of a phase change material to program a selected memory cell. The write driver may be configured to provide the program current such that the program current has a plurality of steps. The control unit may be configured to receive step information for adjusting a magnitude and a width of each step of the program current during a test operation and provide the step information to the write driver during a normal operation.
Abstract translation: 相变存储器件可以包括存储单元阵列，写入驱动器和/或控制单元。 存储单元阵列可以包括多个存储单元。 写入驱动器可以被配置为向存储器单元阵列提供程序电流，用于设置相变材料的状态以对选定的存储单元进行编程。 写驱动器可以被配置为提供程序电流，使得程序电流具有多个步骤。 控制单元可以被配置为在测试操作期间接收用于调整程序电流的每个步骤的幅度和宽度的步骤信息，并且在正常操作期间将该步骤信息提供给写入驱动器。
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公开(公告)号：US20100271868A1
公开(公告)日：2010-10-28
申请号：US12662180
申请日：2010-04-05
Applicant: Mu-Hui Park
Inventor： Mu-Hui Park
CPC classification number: G11C13/0038 , G11C7/04 , G11C13/0004 , G11C13/004 , G11C2013/0045 , G11C2013/0054
Abstract: A phase change memory device includes a memory cell array having a plurality of phase change memory cells, a read bias generating circuit, a clamping circuit and a clamping control signal generating circuit (CCSGC). The read bias generating circuit provides a sensing node with a read bias for reading a resistance level of a selected phase change memory cell. The clamping circuit controls an amount of clamping current flowing into a bit line connected with the selected phase change memory cell. The CCSGC provides the clamping control signal to the clamping circuit and adjusts a level of the clamping control signal.
Abstract translation: 相变存储器件包括具有多个相变存储单元，读偏置产生电路，钳位电路和钳位控制信号发生电路（CCSGC）的存储单元阵列。 读偏置产生电路为感测节点提供读偏置，用于读取所选相变存储单元的电阻电平。 钳位电路控制流入与选择的相变存储单元连接的位线的钳位电流量。 CCSGC向钳位电路提供钳位控制信号，并调整钳位控制信号的电平。
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Patent Agency Ranking
公开(公告)号：US07639558B2
公开(公告)日：2009-12-29
申请号：US11315347
申请日：2005-12-23
Applicant: Beak-hyung Cho , Kwang-jin Lee , Mu-hui Park
Inventor： Beak-hyung Cho , Kwang-jin Lee , Mu-hui Park
CPC classification number: G11C11/5678 , G11C7/12 , G11C13/0004 , G11C13/0028 , G11C2213/72
Abstract: A phase change memory device has a word line driver layout which allows for a reduction in the size a core area of the device. In one aspect, phase change memory device includes a plurality of memory cell blocks sharing a word line, and a plurality of word line drivers driving the word line. Each of the word line drivers includes a precharge device for precharging the word line and a discharge device for discharging the word line, and where the precharge device and the discharge device are alternately located between the plurality of memory cell blocks.
Abstract translation: 相变存储器件具有字线驱动器布局，其允许减小器件的核心区域的尺寸。 一方面，相变存储器件包括共享字线的多个存储单元块和驱动该字线的多个字线驱动器。 每个字线驱动器包括用于对字线预充电的预充电装置和用于放电字线的放电装置，并且其中预充电装置和放电装置交替地位于多个存储单元块之间。
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公开(公告)号：US20080291715A1
公开(公告)日：2008-11-27
申请号：US12116295
申请日：2008-05-07
Applicant: Mu-Hui PARK , Kwang-Jin LEE , Du-Eung KIM , Hye-Jin KIM , Woo-Yeong CHO
Inventor： Mu-Hui PARK , Kwang-Jin LEE , Du-Eung KIM , Hye-Jin KIM , Woo-Yeong CHO
CPC classification number: G11C13/0038 , G11C7/04 , G11C11/5678 , G11C13/0004 , G11C13/004 , G11C29/02 , G11C29/026 , G11C29/028
Abstract: A nonvolatile memory device includes a nonvolatile memory cell, a read circuit and a control bias generating circuit. The nonvolatile memory cell has a resistance level that changes depending on stored data. The read circuit reads the resistance level of the nonvolatile memory cell by receiving a control bias and supplying the nonvolatile memory cell a read bias based on the control bias. The control bias generating circuit receives an input bias, generates the control bias based on the input bias and supplies the control bias to the read circuit. A slope of the control bias to the input bias is less than 1.
Abstract translation: 非易失性存储器件包括非易失性存储单元，读取电路和控制偏置产生电路。 非易失性存储单元具有根据存储的数据而改变的电阻水平。 读取电路通过接收控制偏置来读取非易失性存储单元的电阻电平，并且基于控制偏压向非易失性存储单元提供读取偏置。 控制偏置产生电路接收输入偏置，基于输入偏置产生控制偏压，并将控制偏压提供给读取电路。 对输入偏置的控制偏置的斜率小于1。
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8.发明申请BIAS VOLTAGE GENERATOR AND METHOD GENERATING BIAS VOLTAGE FOR SEMICONDUCTOR MEMORY DEVICE 有权偏置电压发生器和生成半导体存储器件的偏置电压的方法公开(公告)号：US20080159017A1
公开(公告)日：2008-07-03
申请号：US11955562
申请日：2007-12-13
Applicant: Hye-Jin KIM , Kwang-Jin LEE , Woo-Yeong CHO , Mu-Hui PARK
Inventor： Hye-Jin KIM , Kwang-Jin LEE , Woo-Yeong CHO , Mu-Hui PARK
IPC: G11C5/14
CPC classification number: G11C13/004 , G11C5/147 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/0038 , G11C16/30 , G11C2013/0054 , G11C2213/72
Abstract: There are provided a bias voltage generator, a semiconductor memory device having the bias voltage generator, and a method for generating the bias voltage. The bias voltage generator which generates the bias voltage to control a sensing current supplied to a memory cell for sensing data is characterized in that the bias voltage is output in response to an input voltage being applied, so that a slope of the bias voltage to the input voltage is different in at least two sections divided corresponding to a level of the input voltage.
Abstract translation: 提供了偏置电压发生器，具有偏置电压发生器的半导体存储器件以及用于产生偏置电压的方法。 产生用于控制提供给存储单元的感测电流以感测数据的偏置电压的偏置电压发生器的特征在于，响应于所施加的输入电压而输出偏置电压，使得偏置电压的斜率 至少两个部分的输入电压不同，对应于输入电压的电平。
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9.发明申请Non-volatile phase-change memory device and associated program-suspend-read operation 有权非易失性相变存储器件和相关的程序挂起读操作公开(公告)号：US20070217253A1
公开(公告)日：2007-09-20
申请号：US11486100
申请日：2006-07-14
Applicant: Hye-jin Kim , Kwang-jin Lee , Sang-Beom Kang , Mu-hui Park
Inventor： Hye-jin Kim , Kwang-jin Lee , Sang-Beom Kang , Mu-hui Park
IPC: G11C11/00
CPC classification number: G11C8/12 , G11C11/5678 , G11C13/0004 , G11C13/0061 , G11C13/0069 , G11C2013/0078
Abstract: A method of performing a program-suspend-read operation in a PRAM device comprises programming a write block comprising N unit program blocks in response to a program operation request, and suspending the program operation after programming M unit program blocks, where M is less than N, in response to a read operation request. The method further comprises executing the requested read operation, and then resuming the programming of the write data block and programming (N−M) remaining unit program blocks.
Abstract translation: 一种在PRAM设备中执行程序挂起读取操作的方法包括响应于程序操作请求编程包含N个单元程序块的写入块，并且在对M个单元程序块进行编程之后暂停编程操作，其中M小于 N，响应于读取操作请求。 该方法还包括执行所请求的读取操作，然后恢复写入数据块和编程（N-M）剩余单元程序块的编程。
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公开(公告)号：US08320171B2
公开(公告)日：2012-11-27
申请号：US12662180
申请日：2010-04-05
Applicant: Mu-Hui Park
Inventor： Mu-Hui Park
IPC: G11C11/00
CPC classification number: G11C13/0038 , G11C7/04 , G11C13/0004 , G11C13/004 , G11C2013/0045 , G11C2013/0054
Abstract: A phase change memory device includes a memory cell array having a plurality of phase change memory cells, a read bias generating circuit, a clamping circuit and a clamping control signal generating circuit (CCSGC). The read bias generating circuit provides a sensing node with a read bias for reading a resistance level of a selected phase change memory cell. The clamping circuit controls an amount of clamping current flowing into a bit line connected with the selected phase change memory cell. The CCSGC provides the clamping control signal to the clamping circuit and adjusts a level of the clamping control signal.
Abstract translation: 相变存储器件包括具有多个相变存储单元，读偏置产生电路，钳位电路和钳位控制信号发生电路（CCSGC）的存储单元阵列。 读偏置产生电路为感测节点提供读偏置，用于读取所选相变存储单元的电阻电平。 钳位电路控制流入与选择的相变存储单元连接的位线的钳位电流量。 CCSGC向钳位电路提供钳位控制信号，并调整钳位控制信号的电平。
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