发明授权
US08338293B2 Method of reducing erosion of a metal cap layer during via patterning in semiconductor devices
有权
在半导体器件中通孔图案化期间减少金属覆盖层侵蚀的方法
- 专利标题: Method of reducing erosion of a metal cap layer during via patterning in semiconductor devices
- 专利标题(中): 在半导体器件中通孔图案化期间减少金属覆盖层侵蚀的方法
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申请号: US13109639申请日: 2011-05-17
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公开(公告)号: US08338293B2公开(公告)日: 2012-12-25
- 发明人: Christin Bartsch , Daniel Fischer , Matthias Schaller
- 申请人: Christin Bartsch , Daniel Fischer , Matthias Schaller
- 申请人地址: US TX Austin
- 专利权人: Advanced Micro Devies, Inc.
- 当前专利权人: Advanced Micro Devies, Inc.
- 当前专利权人地址: US TX Austin
- 代理机构: Williams, Morgan & Amerson
- 优先权: DE102008021568 20080430
- 主分类号: H01L21/28
- IPC分类号: H01L21/28
摘要:
During the patterning of via openings in sophisticated metallization systems of semiconductor devices, the opening may extend through a conductive cap layer and an appropriate ion bombardment may be established to redistribute material of the underlying metal region to exposed sidewall portions of the conductive cap layer, thereby establishing a protective material. Consequently, in a subsequent wet chemical etch process, the probability for undue material removal of the conductive cap layer may be greatly reduced.
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