公开(公告)号：US08435885B2

公开(公告)日：2013-05-07

申请号：US13180143

申请日：2011-07-11

Applicant: Dmytro Chumakov ,  Petra Hetzer ,  Matthias Schaller

Inventor： Dmytro Chumakov ,  Petra Hetzer ,  Matthias Schaller

IPC: H01L21/4763

CPC classification number: G01N1/04 ,  G01N2001/2833 ,  H01L21/02096

Abstract: Analysis of chemical and physical characteristics of polymer species and etch residues caused in critical plasma-assisted etch processes for patterning material layers in semiconductor devices may be accomplished by removing at least a portion of these species on the basis of a probing material layer, which may be lifted-off from the patterned surface. The probing material layer may substantially suppress a chemical modification of the species of interest and may thus allow the examination of the initial status of these species.

Abstract translation: 可以通过基于探测材料层去除这些物质的至少一部分来实现在半导体器件中的图形材料层的关键等离子体辅助蚀刻工艺中引起的聚合物种类和蚀刻残留物的化学和物理特性的分析， 从图案的表面上脱下来。 探测材料层可以基本上抑制感兴趣物种的化学修饰，并且因此可以允许检查这些物种的初始状态。

公开(公告)号：US20120211837A1

公开(公告)日：2012-08-23

申请号：US13372604

申请日：2012-02-14

Applicant: Peter Baars ,  Till Schloesser ,  Frank Jakubowski ,  Andy Wei ,  Richard Carter ,  Matthias Schaller

Inventor： Peter Baars ,  Till Schloesser ,  Frank Jakubowski ,  Andy Wei ,  Richard Carter ,  Matthias Schaller

IPC: H01L21/28 ,  H01L21/283 ,  H01L27/088

CPC classification number: H01L21/823475 ,  H01L21/28518 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823437 ,  H01L29/66636 ,  H01L29/7848

Abstract: When forming sophisticated semiconductor devices, a replacement gate approach may be applied in combination with a self-aligned contact regime by forming the self-aligned contacts prior to replacing the placeholder material of the gate electrode structures.

Abstract translation: 当形成复杂的半导体器件时，可以在替换栅极电极结构的占位符材料之前形成自对准触点，将替代栅极方法与自对准接触方式结合使用。

公开(公告)号：US20110049713A1

公开(公告)日：2011-03-03

申请号：US12854393

申请日：2010-08-11

Applicant: Kai Frohberg ,  Juergen Boemmels ,  Matthias Schaller ,  Sven Mueller

Inventor： Kai Frohberg ,  Juergen Boemmels ,  Matthias Schaller ,  Sven Mueller

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L29/66659 ,  H01L21/76895 ,  H01L21/823425 ,  H01L21/823475 ,  H01L23/485 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: Contact elements of sophisticated semiconductor devices may be formed for gate electrode structures and for drain and source regions in separate process sequences in order to apply electroless plating techniques without causing undue overfill of one type of contact opening. Consequently, superior process uniformity in combination with a reduced overall contact resistance may be accomplished. In some illustrative embodiments, cobalt may be used as a contact metal without any additional conductive barrier materials.

Abstract translation: 复杂半导体器件的接触元件可以形成用于栅极电极结构和用于分开的工艺序列中的漏极和源极区域，以便施加无电镀技术，而不会导致一种类型的接触开口的不适当的过度填充。 因此，可以实现与降低的总接触电阻相结合的优异的工艺均匀性。 在一些说明性实施例中，钴可以用作接触金属而没有任何额外的导电阻挡材料。

公开(公告)号：US07883629B2

公开(公告)日：2011-02-08

申请号：US11868789

申请日：2007-10-08

Applicant: Matthias Schaller ,  Heike Salz ,  Ralf Richter ,  Sylvio Mattick

Inventor： Matthias Schaller ,  Heike Salz ,  Ralf Richter ,  Sylvio Mattick

IPC: C03C15/00 ,  G01R31/00 ,  H01L21/00 ,  H01L21/66

CPC classification number: H01L21/84 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  H01L22/26 ,  H01L29/7843

Abstract: During the patterning of stressed layers having different types of intrinsic stress, the effects of the deposition of a silicon dioxide based etch indicator material between the first and second dielectric layers may be significantly reduced by a controlled etch on the basis of optical measurement data indicating the etch rate and, thus, the performance of the respective etch process. In other cases, highly efficient etch indicator species may be incorporated into the stressed dielectric layers or may be formed on a surface portion thereof with reduced layer thickness, thereby providing an enhanced endpoint detection signal without creating the negative effects of silicon dioxide based indicator layers. In one illustrative embodiment, a stressed silicon, nitrogen and carbon-containing layer may be combined with a stressed silicon and nitrogen-containing layer, wherein the carbon species provides a prominent endpoint detection signal.

Abstract translation: 在具有不同类型的固有应力的应力层的图案化期间，可以通过基于表示第二和第二电介质层的光学测量数据的受控蚀刻来显着地减少基于二氧化硅的蚀刻指示剂材料沉积的影响 蚀刻速率，因此，各个蚀刻工艺的性能。 在其他情况下，可以将高效的蚀刻指示剂物质结合到应力介电层中，或者可以在其表面部分上形成具有减小的层厚度，从而提供增强的端点检测信号，而不产生基于二氧化硅的指示剂层的负面影响。 在一个说明性实施例中，应力硅，氮和碳的层可以与应力硅和含氮层组合，其中碳类提供突出的端点检测信号。

公开(公告)号：US20100242631A1

公开(公告)日：2010-09-30

申请号：US12725688

申请日：2010-03-17

Applicant: Petra Hetzer ,  Matthias Schaller ,  Dmytro Chumakov

Inventor： Petra Hetzer ,  Matthias Schaller ,  Dmytro Chumakov

IPC: G01N1/04 ,  G01J3/44 ,  B01D59/44 ,  G01J5/02 ,  G01N23/225

CPC classification number: G01N1/02 ,  G01N2001/028 ,  G01N2015/0038 ,  H01L22/12

Abstract: During the fabrication of microstructure devices, such as integrated circuits, particles may be analyzed by displacing or removing the particles from the device surface and subsequently performing an analysis process. Consequently, a well-defined measurement environment may be established after removal of the particles, which may be accomplished on the basis of nanoprobes and the like. Hence, even critical surface areas may be monitored with respect to contamination and the like on the basis of well-established analysis techniques.

Abstract translation: 在诸如集成电路的微结构器件的制造期间，可以通过从器件表面移位或移除颗粒并随后执行分析过程来分析颗粒。 因此，可以在去除颗粒之后建立明确的测量环境，这可以基于纳米探针等来实现。 因此，即使关键的表面积也可以基于已知的分析技术来监测污染等。

公开(公告)号：US07763532B2

公开(公告)日：2010-07-27

申请号：US11145905

申请日：2005-06-06

Applicant: Kai Frohberg ,  Matthias Schaller ,  Roberto Klinger

Inventor： Kai Frohberg ,  Matthias Schaller ,  Roberto Klinger

IPC: H01L21/3205 ,  H01L21/4763 ,  H01L21/44

CPC classification number: H01L21/76837 ,  H01L21/31116 ,  H01L21/76834 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/84 ,  H01L27/1203

Abstract: When forming line structures of semiconductor devices in accordance with the 90 nm technology, sidewall spacers of the lines are reduced in size immediately prior to the deposition of an etch stop layer that is formed on the device layer. Due to the reduced spacer elements or due to a complete removal of the spacer elements, the subsequent deposition of the etch stop layer and of the interlayer dielectric is significantly enhanced with respect to void formation and defect rate.

Abstract translation: 当根据90nm技术形成半导体器件的线结构时，在沉积形成在器件层上的蚀刻停止层之前，线的侧壁间隔物的尺寸被减小。 由于减少的间隔元件或由于间隔元件的完全去除，相对于空隙形成和缺陷率，蚀刻停止层和层间电介质的随后沉积显着增强。

公开(公告)号：US07314793B2

公开(公告)日：2008-01-01

申请号：US11047129

申请日：2005-01-31

Applicant: Kai Frohberg ,  Matthias Schaller ,  Massud Aminpur ,  Martin Mazur ,  Roberto Klingler

Inventor： Kai Frohberg ,  Matthias Schaller ,  Massud Aminpur ,  Martin Mazur ,  Roberto Klingler

IPC: H01L21/8238

CPC classification number: H01L29/6653 ,  H01L21/3215 ,  H01L21/32155 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/7843 ,  Y10S438/938

Abstract: During the formation of a transistor element, sidewalls spacers are removed or at least partially etched back after ion implantation and silicidation, thereby rendering the mechanical coupling of a contact etch stop layer to the underlying drain and source regions more effective. Hence, the mechanical stress may be substantially induced by the contact etch step layer rather than by a combination of the spacer elements and the etch stop layer, thereby significantly facilitating the stress engineering in the channel region. By additionally performing a plasma treatment, different amounts of stress may be created in different transistor devices without unduly contributing to process complexity.

Abstract translation: 在形成晶体管元件期间，在离子注入和硅化之后去除侧壁间隔物或至少部分地回蚀，从而使接触蚀刻停止层与潜在的漏极和源极区域的机械耦合更有效。 因此，机械应力可以基本上由接触蚀刻步骤层引起，而不是间隔元件和蚀刻停止层的组合，从而显着地促进了沟道区域中的应力工程。 通过额外进行等离子体处理，可以在不同的晶体管器件中产生不同量的应力，而不会不利地导致工艺复杂性。

公开(公告)号：US20070178699A1

公开(公告)日：2007-08-02

申请号：US11538860

申请日：2006-10-05

Applicant: Matthias Schaller ,  Uwe Schulze ,  Mathias Baranyai

Inventor： Matthias Schaller ,  Uwe Schulze ,  Mathias Baranyai

IPC: H01L21/302

CPC classification number: H01L21/76808 ,  H01L22/20 ,  H01L2924/0002 ,  Y10T156/1168 ,  H01L2924/00

Abstract: By controlling the flow rate of one or more gaseous components of an etch ambient during the formation of metal lines and vias on the basis of feedback measurement data from critical dimensions, process variations may be reduced, thereby enhancing performance and reliability of the respective metallization structure.

Abstract translation: 通过在基于关键尺寸的反馈测量数据的基础上控制在形成金属线和通孔期间蚀刻环境的一个或多个气体组分的流量，可以减少工艺变化，从而提高各个金属化结构的性能和可靠性 。

公开(公告)号：US20070152343A1

公开(公告)日：2007-07-05

申请号：US11534285

申请日：2006-09-22

Applicant: Ralf Richter ,  Carsten Peters ,  Heike Salz ,  Matthias Schaller

Inventor： Ralf Richter ,  Carsten Peters ,  Heike Salz ,  Matthias Schaller

IPC: H01L23/48 ,  H01L21/4763

CPC classification number: H01L21/76834 ,  H01L21/76832 ,  H01L21/76846 ,  H01L21/76852 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

Abstract: By providing additional etch stop layers and/or etch protection layers, a corresponding etch process for forming contact openings for directly connecting polysilicon lines and active areas may be controlled in a highly reliable manner. Consequently, conductive line erosion and/or penetration into extension regions may be significantly reduced, thereby improving the reliability and performance of corresponding semiconductor devices.

Abstract translation: 通过提供附加的蚀刻停止层和/或蚀刻保护层，可以以高度可靠的方式控制用于形成用于直接连接多晶硅线路和有源区域的接触开口的相应蚀刻工艺。 因此，可以显着地减少导线侵蚀和/或穿透到延伸区域，从而提高对应的半导体器件的可靠性和性能。

公开(公告)号：US20070123009A1

公开(公告)日：2007-05-31

申请号：US11470024

申请日：2006-09-05

Applicant: Ralf Richter ,  Matthias Schaller ,  Ellen Claus ,  Eckhard Langer

Inventor： Ralf Richter ,  Matthias Schaller ,  Ellen Claus ,  Eckhard Langer

IPC: H01L21/20

CPC classification number: H01L23/5226 ,  H01L21/76808 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: By providing dummy vias below electrically non-functional metal regions, the risk for metal delamination in subsequent processes may be significantly reduced. Moreover, in some embodiments, the mechanical strength of the resulting metallization layers may be even more enhanced by providing dummy metal regions, which may act as anchors for an overlying non-functional metal region. In addition, dummy vias may also be provided in combination with electrically functional metal lines and regions, thereby also enhancing the mechanical stability and the electrical performance thereof.

Abstract translation: 通过在电气非功能金属区域之下提供虚拟通孔，可以显着降低后续工艺中金属分层的风险。 而且，在一些实施例中，所得到的金属化层的机械强度甚至可以通过提供虚拟金属区域来进一步增强，虚拟金属区域可以用作覆盖的非功能性金属区域的锚点。 此外，还可以与电功能金属线和区域组合提供虚拟通孔，从而也增强机械稳定性及其电性能。