Invention Grant
- Patent Title: Systems and methods for reducing frequency pulling in an oscillator circuit
- Patent Title (中): 降低振荡电路中牵引频率的系统和方法
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Application No.: US12914235Application Date: 2010-10-28
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Publication No.: US08354890B2Publication Date: 2013-01-15
- Inventor: Yuyu Chang , John Leete , Walid Ahmed , Wei Luo
- Applicant: Yuyu Chang , John Leete , Walid Ahmed , Wei Luo
- Applicant Address: US CA Irvine
- Assignee: Broadcom Corporation
- Current Assignee: Broadcom Corporation
- Current Assignee Address: US CA Irvine
- Agency: Sterne, Kessler, Goldstein & Fox PLLC
- Main IPC: H03B1/00
- IPC: H03B1/00 ; H03B5/32

Abstract:
Methods and systems are provided to calibrate an oscillator circuit to reduce frequency pulling as a result of a change in power to a portion of the oscillator circuit. In an embodiment, an oscillator is coupled to a clock buffer circuit and a tuning capacitor configured to tune a frequency of the oscillator to a baseline frequency required for cellular communications. A change in power to the clock buffer circuit initiates a change in an amount of capacitance seen by the oscillator, which negatively impacts the tuning of the oscillator. A register stores a frequency offset caused by the change in power, and the tuning capacitor is adjusted, using the frequency offset, in response to the change in power, such that the total amount of capacitance seen by the oscillator is not changed when the change in power occurs.
Public/Granted literature
- US20120068780A1 Systems and Methods for Reducing Frequency Pulling in an Oscillator Circuit Public/Granted day:2012-03-22
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