To improve reliability of a semiconductor device having an SRAM.The semiconductor device has a memory cell including six n-channel type transistors and two p-channel type transistors formed over a silicon substrate. Over the silicon substrate, a first p well, a first n well, a second p well, a second n well, and a third p well are arranged in this order when viewed in a row direction. First and second positive-phase access transistors are disposed in the first p well, first and second driver transistors are disposed in the second p well, and first and second negative-phase access transistors are arranged in the third p well.