发明授权
- 专利标题: Semiconductor substrate planarization apparatus and planarization method
- 专利标题(中): 半导体衬底平面化装置和平面化方法
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申请号: US12748109申请日: 2010-03-26
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公开(公告)号: US08366514B2公开(公告)日: 2013-02-05
- 发明人: Satoru Ide , Moriyuki Kashiwa , Kazuo Kobayashi , Noriyuki Motimaru , Eiichi Yamamoto , Tomio Kubo , Hiroaki Kida
- 申请人: Satoru Ide , Moriyuki Kashiwa , Kazuo Kobayashi , Noriyuki Motimaru , Eiichi Yamamoto , Tomio Kubo , Hiroaki Kida
- 申请人地址: JP Annaka
- 专利权人: Okamoto Machine Tool Works, Ltd.
- 当前专利权人: Okamoto Machine Tool Works, Ltd.
- 当前专利权人地址: JP Annaka
- 代理机构: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- 优先权: JP2010-001727 20100107
- 主分类号: B24B1/00
- IPC分类号: B24B1/00 ; B24B5/02
摘要:
A planarization apparatus and method that thins and planarizes a substrate by grinding and polishing the rear surface of the substrate with high throughput, and that fabricates a semiconductor substrate with reduced adhered contaminants. A planarization apparatus that houses various mechanism elements in semiconductor substrate loading/unloading stage chamber, a rear-surface polishing stage chamber, and a rear-surface grinding stage chamber. The throughput time of the rear-surface polishing stage that simultaneously polishes two substrates is typically about double the throughput time of the rear-surface grinding stage that grinds one substrate.