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US08392861B2 Method of semiconductor integrated circuit device using library for estimating timing/area to place cells 有权
用于估计定时/面积放置单元的库的半导体集成电路器件的方法

Method of semiconductor integrated circuit device using library for estimating timing/area to place cells
摘要:
To considerably reduce the cell layout change after timing optimization to reduce the term of layout design by estimating timing and an area after the timing optimization. During the period of initial layout processing using a net list, a timing constraint, a floor plan, a layout library, a timing library, etc., a library for estimating timing/area for estimating the timing and area after the timing optimization is created in advance and whether the timing constraint can be met is estimated. A cell in a path that hardly meets the timing constraint is placed in proximity and conversely, a cell that easily meets the timing constraint is placed at a distance. At this time, an area increase is also estimated so that wiring congestion does not occur.
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