发明授权
US08392861B2 Method of semiconductor integrated circuit device using library for estimating timing/area to place cells
有权
用于估计定时/面积放置单元的库的半导体集成电路器件的方法
- 专利标题: Method of semiconductor integrated circuit device using library for estimating timing/area to place cells
- 专利标题(中): 用于估计定时/面积放置单元的库的半导体集成电路器件的方法
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申请号: US13046752申请日: 2011-03-13
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公开(公告)号: US08392861B2公开(公告)日: 2013-03-05
- 发明人: Satoshi Shibatani , Ryoji Ishikawa , Kenta Suto
- 申请人: Satoshi Shibatani , Ryoji Ishikawa , Kenta Suto
- 申请人地址: JP Kawasaki-shi
- 专利权人: Renesas Electronics Corporation
- 当前专利权人: Renesas Electronics Corporation
- 当前专利权人地址: JP Kawasaki-shi
- 代理机构: Miles and Stockbridge P.C.
- 优先权: JP2010-074219 20100329
- 主分类号: G06F17/50
- IPC分类号: G06F17/50
摘要:
To considerably reduce the cell layout change after timing optimization to reduce the term of layout design by estimating timing and an area after the timing optimization. During the period of initial layout processing using a net list, a timing constraint, a floor plan, a layout library, a timing library, etc., a library for estimating timing/area for estimating the timing and area after the timing optimization is created in advance and whether the timing constraint can be met is estimated. A cell in a path that hardly meets the timing constraint is placed in proximity and conversely, a cell that easily meets the timing constraint is placed at a distance. At this time, an area increase is also estimated so that wiring congestion does not occur.
公开/授权文献
- US20110239179A1 DESIGN METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 公开/授权日:2011-09-29
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