公开(公告)号：US08392861B2

公开(公告)日：2013-03-05

申请号：US13046752

申请日：2011-03-13

申请人： Satoshi Shibatani ,  Ryoji Ishikawa ,  Kenta Suto

发明人： Satoshi Shibatani ,  Ryoji Ishikawa ,  Kenta Suto

IPC分类号： G06F17/50

CPC分类号： G06F17/5072 ,  G06F17/5031 ,  G06F2217/84

摘要： To considerably reduce the cell layout change after timing optimization to reduce the term of layout design by estimating timing and an area after the timing optimization. During the period of initial layout processing using a net list, a timing constraint, a floor plan, a layout library, a timing library, etc., a library for estimating timing/area for estimating the timing and area after the timing optimization is created in advance and whether the timing constraint can be met is estimated. A cell in a path that hardly meets the timing constraint is placed in proximity and conversely, a cell that easily meets the timing constraint is placed at a distance. At this time, an area increase is also estimated so that wiring congestion does not occur.

摘要翻译： 为了大大减少定时优化后的单元布局变化，通过估计定时和定时优化后的面积来减少布局设计的期限。 在使用网表，定时约束，平面图，布局库，定时库等的初始布局处理期间，创建用于估计定时优化之后的定时和区域的定时/区域的库 估计是否可以满足时序约束。 几乎不能满足时序约束的路径中的单元被置于接近的位置，相反地，容易满足定时约束的单元被放置在一定距离处。 此时，还估计区域增加，使得不发生布线拥塞。

公开(公告)号：US08434042B2

公开(公告)日：2013-04-30

申请号：US13141986

申请日：2008-12-26

申请人： Ryoji Ishikawa

发明人： Ryoji Ishikawa

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： In order to improve a failure detection rate in a layout automatic design process of a DFT circuit, signal lines of the DFT circuit are aggregated by an AND tree circuit 1 or an OR tree circuit instead of an EXOR tree circuit, and outputs thereof are received by an observation flip-flop 2. When a failure detection process of the DFT circuit is performed by using the EXOR tree circuit in the case where partial circuits outputting respective signal lines are shared or the partial circuits have the same structure, the signals cancel each other and the failures of the original partial circuits cannot be detected in some cases. However, such a trouble can be prevented by using the AND tree circuit 1 or the OR tree circuit instead of the EXOR tree circuit.

摘要翻译： 为了提高DFT电路的布局自动设计处理中的故障检测率，DFT电路的信号线由AND树电路1或OR树电路代替EXOR树电路聚合，并且其输出被接收 通过观察触发器2.当在共享输出各个信号线的部分电路或者部分电路具有相同结构的情况下通过使用EXOR树电路来执行DFT电路的故障检测处理时，该信号取消每个 在某些情况下，不能检测到原始部分电路的其他故障和故障。 然而，可以通过使用AND树电路1或OR树电路代替EXOR树电路来防止这种麻烦。

公开(公告)号：US08621415B2

公开(公告)日：2013-12-31

申请号：US13372434

申请日：2012-02-13

申请人： Kenta Suto ,  Satoshi Shibatani ,  Ryoji Ishikawa ,  Ken Saito ,  Yoshio Inoue

发明人： Kenta Suto ,  Satoshi Shibatani ,  Ryoji Ishikawa ,  Ken Saito ,  Yoshio Inoue

IPC分类号： G06F17/50

CPC分类号： G06F17/5022 ,  G06F17/5068 ,  G06F2217/78 ,  G06F2217/84

摘要： A power domain is automatically generated.A computer performs a function simulation process 9 for evaluating whether or not a designed circuit satisfies a specification, and a clustering process 10 which obtains a power domain by clustering logical blocks in which activation timings are within a range, based on the result of the function simulation process. Since the power domain is obtained by a process performed by the computer, the power domain can be optimized compared to a case when it is obtained by hand (manual work of the designer).

摘要翻译： 电源域自动生成。 计算机执行功能模拟处理9，用于评估设计的电路是否满足规格;以及聚类处理10，其基于功能的结果，通过对激活定时在一定范围内的逻辑块进行聚类而获得功率域 模拟过程。 由于通过计算机执行的处理获得功率域，所以与通过手动（设计人员的手工工作）获得的情况相比，能够优化功率域。

公开(公告)号：US20110265053A1

公开(公告)日：2011-10-27

申请号：US13141986

申请日：2008-12-26

申请人： Ryoji Ishikawa

发明人： Ryoji Ishikawa

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： In order to improve a failure detection rate in a layout automatic design process of a DFT circuit, signal lines of the DFT circuit are aggregated by an AND tree circuit 1 or an OR tree circuit instead of an EXOR tree circuit, and outputs thereof are received by an observation flip-flop 2. When a failure detection process of the DFT circuit is performed by using the EXOR tree circuit in the case where partial circuits outputting respective signal lines are shared or the partial circuits have the same structure, the signals cancel each other and the failures of the original partial circuits cannot be detected in some cases. However, such a trouble can be prevented by using the AND tree circuit 1 or the OR tree circuit instead of the EXOR tree circuit.

摘要翻译： 为了提高DFT电路的布局自动设计处理中的故障检测率，DFT电路的信号线由AND树电路1或OR树电路代替EXOR树电路聚合，并且其输出被接收 通过观察触发器2.当在共享输出各个信号线的部分电路或者部分电路具有相同结构的情况下通过使用EXOR树电路来执行DFT电路的故障检测处理时，该信号取消每个 在某些情况下，不能检测到原始部分电路的其他故障和故障。 然而，可以通过使用AND树电路1或OR树电路代替EXOR树电路来防止这种麻烦。

公开(公告)号：US20120216166A1

公开(公告)日：2012-08-23

申请号：US13372434

申请日：2012-02-13

申请人： Kenta SUTO ,  Satoshi Shibatani ,  Ryoji Ishikawa ,  Ken Saito ,  Yoshio Inoue

发明人： Kenta SUTO ,  Satoshi Shibatani ,  Ryoji Ishikawa ,  Ken Saito ,  Yoshio Inoue

IPC分类号： G06F17/50

CPC分类号： G06F17/5022 ,  G06F17/5068 ,  G06F2217/78 ,  G06F2217/84

摘要： A power domain is automatically generated.A computer performs a function simulation process 9 for evaluating whether or not a designed circuit satisfies a specification, and a clustering process 10 which obtains a power domain by clustering logical blocks in which activation timings are within a range, based on the result of the function simulation process. Since the power domain is obtained by a process performed by the computer, the power domain can be optimized compared to a case when it is obtained by hand (manual work of the designer).

摘要翻译： 电源域自动生成。 计算机执行功能模拟处理9，用于评估设计的电路是否满足规格;以及聚类处理10，其基于功能的结果，通过对激活定时在一定范围内的逻辑块进行聚类而获得功率域 模拟过程。 由于通过计算机执行的处理获得功率域，所以与通过手动（设计人员的手工工作）获得的情况相比，能够优化功率域。

公开(公告)号：US20110239179A1

公开(公告)日：2011-09-29

申请号：US13046752

申请日：2011-03-13

申请人： Satoshi SHIBATANI ,  Ryoji ISHIKAWA ,  Kenta SUTO

发明人： Satoshi SHIBATANI ,  Ryoji ISHIKAWA ,  Kenta SUTO

IPC分类号： G06F17/50

CPC分类号： G06F17/5072 ,  G06F17/5031 ,  G06F2217/84

摘要： To considerably reduce the cell layout change after timing optimization to reduce the term of layout design by estimating timing and an area after the timing optimization.During the period of initial layout processing using a net list, a timing constraint, a floor plan, a layout library, a timing library, etc., a library for estimating timing/area for estimating the timing and area after the timing optimization is created in advance and whether the timing constraint can be met is estimated. A cell in a path that hardly meets the timing constraint is placed in proximity and conversely, a cell that easily meets the timing constraint is placed at a distance. At this time, an area increase is also estimated so that wiring congestion does not occur.

摘要翻译： 为了大大减少定时优化后的单元布局变化，通过估计定时和定时优化后的面积来减少布局设计的期限。 在使用网表，定时约束，平面图，布局库，定时库等的初始布局处理期间，创建用于估计定时优化之后的定时和区域的定时/区域的库 估计是否可以满足时序约束。 几乎不能满足时序约束的路径中的单元被置于接近的位置，相反地，容易满足定时约束的单元被放置在一定距离处。 此时，还估计区域增加，使得不发生布线拥塞。