发明授权
US08397238B2 Thread allocation and clock cycle adjustment in an interleaved multi-threaded processor
有权
交错多线程处理器中的线程分配和时钟周期调整
- 专利标题： Thread allocation and clock cycle adjustment in an interleaved multi-threaded processor
- 专利标题（中）： 交错多线程处理器中的线程分配和时钟周期调整
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申请号： US12632873申请日： 2009-12-08
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公开(公告)号： US08397238B2公开(公告)日： 2013-03-12
- 发明人: Suresh K. Venkumahanti , Martin Saint-Laurent , Lucian Codrescu , Baker S. Mohammad
- 申请人： Suresh K. Venkumahanti , Martin Saint-Laurent , Lucian Codrescu , Baker S. Mohammad
- 申请人地址： US CA San Diego
- 专利权人： QUALCOMM Incorporated
- 当前专利权人： QUALCOMM Incorporated
- 当前专利权人地址： US CA San Diego
- 代理商 Peter M. Kamarchik; Nicholas J. Pauley; Jonathan T. Velasco
- 主分类号： G06F9/46
- IPC分类号： G06F9/46
摘要：
Methods, apparatuses, and computer-readable storage media are disclosed for reducing power by reducing hardware-thread toggling in a multi-threaded processor. In a particular embodiment, a method allocates software threads to hardware threads. A number of software threads to be allocated is identified. It is determined when the number of software threads is less than a number of hardware threads. When the number of software threads is less than the number of hardware threads, at least two of the software threads are allocated to non-sequential hardware threads. A clock signal to be applied to the hardware threads is adjusted responsive to the non-sequential hardware threads allocated.