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1.发明申请Thread Allocation and Clock Cycle Adjustment in an Interleaved Multi-Threaded Processor 有权交错多线程处理器中的线程分配和时钟周期调整公开(公告)号：US20110138393A1
公开(公告)日：2011-06-09
申请号：US12632873
申请日：2009-12-08
CPC分类号： G01R1/07378 , G01R3/00 , G01R31/2846 , G01R31/2889 , G01R31/2896 , G06F9/3851
摘要： Methods, apparatuses, and computer-readable storage media are disclosed for reducing power by reducing hardware-thread toggling in a multi-threaded processor. In a particular embodiment, a method allocates software threads to hardware threads. A number of software threads to be allocated is identified. It is determined when the number of software threads is less than a number of hardware threads. When the number of software threads is less than the number of hardware threads, at least two of the software threads are allocated to non-sequential hardware threads. A clock signal to be applied to the hardware threads is adjusted responsive to the non-sequential hardware threads allocated.
摘要翻译： 公开了用于通过减少多线程处理器中的硬件线程切换来降低功率的方法，装置和计算机可读存储介质。 在特定实施例中，一种方法将软件线程分配给硬件线程。 识别要分配的多个软件线程。 何时软件线程的数量少于多个硬件线程。 当软件线程的数量小于硬件线程数时，至少两个软件线程被分配给非顺序硬件线程。 响应于所分配的非顺序硬件线程来调整应用于硬件线程的时钟信号。
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2.发明授权Thread allocation and clock cycle adjustment in an interleaved multi-threaded processor 有权交错多线程处理器中的线程分配和时钟周期调整公开(公告)号：US08397238B2
公开(公告)日：2013-03-12
申请号：US12632873
申请日：2009-12-08
IPC分类号： G06F9/46
CPC分类号： G01R1/07378 , G01R3/00 , G01R31/2846 , G01R31/2889 , G01R31/2896 , G06F9/3851
摘要： Methods, apparatuses, and computer-readable storage media are disclosed for reducing power by reducing hardware-thread toggling in a multi-threaded processor. In a particular embodiment, a method allocates software threads to hardware threads. A number of software threads to be allocated is identified. It is determined when the number of software threads is less than a number of hardware threads. When the number of software threads is less than the number of hardware threads, at least two of the software threads are allocated to non-sequential hardware threads. A clock signal to be applied to the hardware threads is adjusted responsive to the non-sequential hardware threads allocated.
摘要翻译： 公开了用于通过减少多线程处理器中的硬件线程切换来降低功率的方法，装置和计算机可读存储介质。 在特定实施例中，一种方法将软件线程分配给硬件线程。 识别要分配的多个软件线程。 何时软件线程的数量少于多个硬件线程。 当软件线程的数量小于硬件线程数时，至少两个软件线程被分配给非顺序硬件线程。 响应于所分配的非顺序硬件线程来调整应用于硬件线程的时钟信号。
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公开(公告)号：US20130076424A1
公开(公告)日：2013-03-28
申请号：US13242469
申请日：2011-09-23
IPC分类号： H03H11/26
CPC分类号： G06F13/4077 , G06F13/4072 , G06F13/4291 , H03K3/356069 , H03K3/356113 , H03K5/15 , Y02D10/14 , Y02D10/151
摘要： A device includes a plurality of driver circuits coupled to a plurality of bus lines. A first driver circuit of the plurality of driver circuits is coupled to a first bus line of the plurality of bus lines. The first driver circuit includes one of a skewed inverter, a level shifter, a latch, and a sense amplifier configured to produce an output signal that transitions after a first delay in response to a first digital value transition of an input signal from high to low and transitions after a second delay in response to a second digital value transition of the input signal from low to high. The first delay is different from the second delay by an amount sufficient to reduce power related to transmission of signals over the first bus line and over a second bus line in close physical proximity to the first bus line.
摘要翻译： 一种装置包括耦合到多条总线线路的多个驱动电路。 多个驱动器电路的第一驱动电路耦合到多条总线的第一总线。 第一驱动器电路包括偏置反相器，电平移位器，锁存器和读出放大器之一，其被配置为产生响应于输入信号从高到低的第一数字值转换的第一延迟之后转变的输出信号 并且响应于输入信号从低到高的第二数字值转换而在第二延迟之后转变。 第一延迟与第二延迟不同，其量足以减少与第一总线线路上的信号的传输相关的功率，并且在与第一总线线路紧密接近的第二总线上。
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公开(公告)号：US20110215827A1
公开(公告)日：2011-09-08
申请号：US12716341
申请日：2010-03-03
申请人： Baker S. Mohammad , Hong S. Kim , Paul D. Bassett
发明人： Baker S. Mohammad , Hong S. Kim , Paul D. Bassett
IPC分类号： G01R31/26
CPC分类号： G01R31/2642 , G11C11/41 , G11C29/12 , G11C29/50
摘要： In a particular embodiment, a method includes receiving a testing activation signal at a controller coupled to a semiconductor device. The method further includes biasing a well of at least one transistor of the semiconductor device in response to the received testing activation signal. The bias is provided by a biasing circuit that is responsive to the controller. While the well is biased, a test of the semiconductor device is performed to generate testing data.
摘要翻译： 在特定实施例中，一种方法包括在耦合到半导体器件的控制器处接收测试激活信号。 该方法还包括响应于所接收的测试激活信号来偏置半导体器件的至少一个晶体管的阱。 该偏压由对控制器作出响应的偏置电路提供。 当井被偏置时，执行半导体器件的测试以产生测试数据。
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公开(公告)号：US08466707B2
公开(公告)日：2013-06-18
申请号：US12716341
申请日：2010-03-03
IPC分类号： G01R31/02
CPC分类号： G01R31/2642 , G11C11/41 , G11C29/12 , G11C29/50
摘要： In a particular embodiment, a method includes receiving a testing activation signal at a controller coupled to a semiconductor device. The method further includes biasing a well of at least one transistor of the semiconductor device in response to the received testing activation signal. The bias is provided by a biasing circuit that is responsive to the controller. While the well is biased, a test of the semiconductor device is performed to generate testing data.
摘要翻译： 在特定实施例中，一种方法包括在耦合到半导体器件的控制器处接收测试激活信号。 该方法还包括响应于所接收的测试激活信号来偏置半导体器件的至少一个晶体管的阱。 该偏压由对控制器作出响应的偏置电路提供。 当井被偏置时，执行半导体器件的测试以产生测试数据。
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6.发明申请System and Method to Read a Memory Cell with a Complementary Metal-Oxide-Semiconductor (CMOS) Read Transistor 有权使用互补金属氧化物半导体（CMOS）读取晶体管读取存储单元的系统和方法公开(公告)号：US20110273943A1
公开(公告)日：2011-11-10
申请号：US12774181
申请日：2010-05-05
申请人： Baker S. Mohammad
发明人： Baker S. Mohammad
CPC分类号： G11C11/419 , G11C11/412
摘要： A system and method to manage leakage of a complementary metal-oxide-semiconductor (CMOS) read transistor in a memory cell. In a particular embodiment, a memory cell is disclosed that includes a storage element and a complementary metal-oxide-semiconductor (CMOS) read transistor. The CMOS read transistor includes a first terminal coupled to a read word line, a second terminal coupled to a read bit line, and a third terminal coupled to the storage element. During a non-read operating time, the read word line and the read bit line are both maintained at substantially the same voltage level. During a read operation, the read word line is maintained at a particular voltage level until after a voltage representing data stored at the storage element is sensed by the CMOS read transistor.
摘要翻译： 一种用于管理存储器单元中互补金属氧化物半导体（CMOS）读取晶体管的泄漏的系统和方法。 在特定实施例中，公开了一种存储单元，其包括存储元件和互补金属氧化物半导体（CMOS）读取晶体管。 CMOS读取晶体管包括耦合到读取字线的第一端子，耦合到读取位线的第二端子和耦合到存储元件的第三端子。 在非读取操作时间期间，读取字线和读取位线都保持在基本上相同的电压电平。 在读取操作期间，读取的字线被维持在特定的电压电平，直到表示存储在存储元件中的数据的电压被CMOS读取晶体管感测到。
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7.发明授权System and method to read a memory cell with a complementary metal-oxide-semiconductor (CMOS) read transistor 有权用互补金属氧化物半导体（CMOS）读取晶体管读取存储单元的系统和方法公开(公告)号：US08737117B2
公开(公告)日：2014-05-27
申请号：US12774181
申请日：2010-05-05
申请人： Baker S. Mohammad
发明人： Baker S. Mohammad
IPC分类号： G11C11/412
CPC分类号： G11C11/419 , G11C11/412
摘要： A system and method to manage leakage of a complementary metal-oxide-semiconductor (CMOS) read transistor in a memory cell. In a particular embodiment, a memory cell is disclosed that includes a storage element and a complementary metal-oxide-semiconductor (CMOS) read transistor. The CMOS read transistor includes a first terminal coupled to a read word line, a second terminal coupled to a read bit line, and a third terminal coupled to the storage element. During a non-read operating time, the read word line and the read bit line are both maintained at substantially the same voltage level. During a read operation, the read word line is maintained at a particular voltage level until after a voltage representing data stored at the storage element is sensed by the CMOS read transistor.
摘要翻译： 一种用于管理存储器单元中互补金属氧化物半导体（CMOS）读取晶体管的泄漏的系统和方法。 在特定实施例中，公开了一种存储单元，其包括存储元件和互补金属氧化物半导体（CMOS）读取晶体管。 CMOS读取晶体管包括耦合到读取字线的第一端子，耦合到读取位线的第二端子和耦合到存储元件的第三端子。 在非读取操作时间期间，读取字线和读取位线都保持在基本上相同的电压电平。 在读取操作期间，读取的字线被维持在特定的电压电平，直到表示存储在存储元件中的数据的电压被CMOS读取晶体管感测到。
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