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1.发明申请Thread Allocation and Clock Cycle Adjustment in an Interleaved Multi-Threaded Processor 有权交错多线程处理器中的线程分配和时钟周期调整公开(公告)号：US20110138393A1
公开(公告)日：2011-06-09
申请号：US12632873
申请日：2009-12-08
CPC分类号： G01R1/07378 , G01R3/00 , G01R31/2846 , G01R31/2889 , G01R31/2896 , G06F9/3851
摘要： Methods, apparatuses, and computer-readable storage media are disclosed for reducing power by reducing hardware-thread toggling in a multi-threaded processor. In a particular embodiment, a method allocates software threads to hardware threads. A number of software threads to be allocated is identified. It is determined when the number of software threads is less than a number of hardware threads. When the number of software threads is less than the number of hardware threads, at least two of the software threads are allocated to non-sequential hardware threads. A clock signal to be applied to the hardware threads is adjusted responsive to the non-sequential hardware threads allocated.
摘要翻译： 公开了用于通过减少多线程处理器中的硬件线程切换来降低功率的方法，装置和计算机可读存储介质。 在特定实施例中，一种方法将软件线程分配给硬件线程。 识别要分配的多个软件线程。 何时软件线程的数量少于多个硬件线程。 当软件线程的数量小于硬件线程数时，至少两个软件线程被分配给非顺序硬件线程。 响应于所分配的非顺序硬件线程来调整应用于硬件线程的时钟信号。
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公开(公告)号：US07911239B2
公开(公告)日：2011-03-22
申请号：US11453733
申请日：2006-06-14
申请人： Martin Saint-Laurent , Yan Zhang
发明人： Martin Saint-Laurent , Yan Zhang
CPC分类号： H04L7/0083 , G06F1/08
摘要： Techniques for the design and use of a digital signal processor, including for processing transmissions in a communications system. Reduced glitch occurs in switching from a first clock input to a second clock input driving a clock multiplexer. The clock multiplexer receives a first clock input and provides a clock output and determines a low phase output level in the clock output. For a limited period of time, a low phase output level is forced. The clock multiplexer receives a second clock input and determines a low phase input level in the second clock input signal. Switching to providing the clock output in response to the second clock input occurs during the low phase input level in the second clock input signal. Then, the output of the clock multiplexer follows the phase level of the second clock signal.
摘要翻译： 用于设计和使用数字信号处理器的技术，包括用于处理通信系统中的传输。 在从第一时钟输入切换到驱动时钟多路复用器的第二时钟输入时发生减小的毛刺。 时钟多路复用器接收第一时钟输入并提供时钟输出并确定时钟输出中的低相位输出电平。 在有限的时间段内，强制执行低相输出电平。 时钟复用器接收第二时钟输入并确定第二时钟输入信号中的低相位输入电平。 响应于第二时钟输入而提供时钟输出的切换发生在第二时钟输入信号中的低相位输入电平期间。 然后，时钟复用器的输出跟随第二时钟信号的相位电平。
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公开(公告)号：US20090267649A1
公开(公告)日：2009-10-29
申请号：US12431992
申请日：2009-04-29
IPC分类号： H03K19/096 , H03K19/00
CPC分类号： H03K19/0016 , G06F1/04
摘要： A clock gating system and method is disclosed. In a particular embodiment, the system includes an input logic circuit having at least one input to receive at least one input signal and having an output at an internal enable node. A keeper circuit includes at least one switching element that is responsive to a gated clock signal and is coupled to the internal enable node to selectively hold a logical voltage level at the internal enable node. The system further includes a gating element responsive to an input clock signal and to the logical voltage level at the internal enable node to generate the gated clock signal.
摘要翻译： 公开了时钟选通系统和方法。 在特定实施例中，系统包括输入逻辑电路，该输入逻辑电路具有至少一个输入端以接收至少一个输入信号并在内部使能节点具有输出。 保持器电路包括响应于门控时钟信号的至少一个开关元件，并且耦合到内部使能节点以选择性地保持内部使能节点处的逻辑电压电平。 该系统还包括响应于输入时钟信号和内部使能节点处的逻辑电压电平的选通元件，以产生门控时钟信号。
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公开(公告)号：US07567096B2
公开(公告)日：2009-07-28
申请号：US11843696
申请日：2007-08-23
IPC分类号： H03K19/096
CPC分类号： H03K19/0016 , H03K19/001
摘要： In particular illustrative embodiments, circuit devices and methods of controlling a voltage swing are disclosed. The method includes receiving a signal at an input of a digital circuit device including a capacitive node. The method also includes selectively activating a voltage level adjustment element to regulate an electrical discharge path from the capacitive node to an electrical ground to prevent complete discharge of the capacitive node. In a particular illustrative embodiment, the received signal may be a clock signal.
摘要翻译： 在具体说明性实施例中，公开了电路装置和控制电压摆幅的方法。 该方法包括在包括电容性节点的数字电路装置的输入处接收信号。 该方法还包括选择性地激活电压电平调节元件以调节从电容节点到电接地的放电路径，以防止电容性节点的完全放电。 在特定说明性实施例中，接收信号可以是时钟信号。
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公开(公告)号：US20070290725A1
公开(公告)日：2007-12-20
申请号：US11453733
申请日：2006-06-14
申请人： Martin Saint-Laurent , Yan Zhang
发明人： Martin Saint-Laurent , Yan Zhang
IPC分类号： G06F1/08
CPC分类号： H04L7/0083 , G06F1/08
摘要： Techniques for the design and use of a digital signal processor, including (but not limited to) for processing transmissions in a communications (e.g., CDMA) system. Reduced glitch occurs in switching from a first clock input to a second clock input driving a clock multiplexer. The clock multiplexer receives a first clock input and provides a clock output and determines a low phase output level in the clock output in response to a low phase input level in the first clock output. For a limited period of time, a low phase output level is forced irrespective of the phase level of the first clock input signal. The clock multiplexer receives a second clock input and determines a low phase input level in the second clock input signal. Switching to providing the clock output in response to the second clock input occurs during the low phase input level in the second clock input signal. Then, the output of the clock multiplexer follows the phase level of the second clock signal.
摘要翻译： 用于设计和使用数字信号处理器的技术，包括（但不限于）用于处理通信（例如，CDMA）系统中的传输。 在从第一时钟输入切换到驱动时钟多路复用器的第二时钟输入时发生减小的毛刺。 时钟多路复用器接收第一时钟输入并提供时钟输出，并响应于第一时钟输出中的低相位输入电平确定时钟输出中的低相位输出电平。 在有限的时间段内，不管第一时钟输入信号的相位电平如何，都会强制执行低相输出电平。 时钟复用器接收第二时钟输入并确定第二时钟输入信号中的低相位输入电平。 响应于第二时钟输入而提供时钟输出的切换发生在第二时钟输入信号中的低相位输入电平期间。 然后，时钟复用器的输出跟随第二时钟信号的相位电平。
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公开(公告)号：US08995207B2
公开(公告)日：2015-03-31
申请号：US13208450
申请日：2011-08-12
CPC分类号： G06F5/06 , G06F5/10 , G06F5/14 , G06F2205/102 , G11C5/145
摘要： According to an embodiment, an apparatus includes a data storage device. Data to be stored in the data storage device is level shifted from a first voltage domain to a second voltage domain prior to being stored within the data storage device. The data storage device is powered by the second voltage domain. The apparatus further includes a circuit that is powered by the second voltage domain and that is responsive to data output by the data storage device.
摘要翻译： 根据实施例，一种装置包括数据存储装置。 要存储在数据存储设备中的数据在被存储在数据存储设备中之前从第一电压域电平移位到第二电压域。 数据存储设备由第二电压域供电。 该装置还包括由第二电压域供电并且响应于数据存储装置输出的数据的电路。
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公开(公告)号：US07996695B2
公开(公告)日：2011-08-09
申请号：US12032059
申请日：2008-02-15
申请人： Martin Saint-Laurent , Jentsung Lin
发明人： Martin Saint-Laurent , Jentsung Lin
IPC分类号： G06F1/00
CPC分类号： H03K19/0016
摘要： A circuit for reducing sleep state current leakage is described. The circuit includes a hardware unit selected from at least one of a latch, a flip-flop, a comparator, a multiplexer, or an adder. The hardware unit includes a first node. The hardware unit further includes a sleep enabled combinational logic coupled to the first node, wherein a value of the first node is preserved during a sleep state.
摘要翻译： 描述了一种用于降低睡眠状态电流泄漏的电路。 该电路包括从锁存器，触发器，比较器，多路复用器或加法器中的至少一个中选择的硬件单元。 硬件单元包括第一节点。 硬件单元还包括耦合到第一节点的启用睡眠的组合逻辑，其中在睡眠状态期间保留第一节点的值。
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公开(公告)号：US20090058463A1
公开(公告)日：2009-03-05
申请号：US11845950
申请日：2007-08-28
IPC分类号： H03K3/02
CPC分类号： H03K3/356121 , G06F9/3869
摘要： A method is disclosed that includes propagating data via a first data path of a sequential circuit element in response to a clock signal received at a single clocked transistor of the sequential circuit element. The method also includes retaining information related to the data propagated via the first path at a retention circuit element of a second data path, where the first data path includes a first transistor that is responsive to an output of the single clocked transistor. The first transistor has a higher current flow capacity than a second transistor associated with the second data path.
摘要翻译： 公开了一种方法，其包括响应于在顺序电路元件的单个时钟晶体管处接收的时钟信号，经由时序电路元件的第一数据路径传播数据。 该方法还包括保持与在第二数据路径的保持电路元件处经由第一路径传播的数据有关的信息，其中第一数据路径包括响应于单个时钟晶体管的输出的第一晶体管。 第一晶体管具有比与第二数据路径相关联的第二晶体管更高的电流流动能力。
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公开(公告)号：US20080231322A1
公开(公告)日：2008-09-25
申请号：US11843696
申请日：2007-08-23
IPC分类号： H03K19/0175
CPC分类号： H03K19/0016 , H03K19/001
摘要： In particular illustrative embodiments, circuit devices and methods of controlling a voltage swing are disclosed. The method includes receiving a signal at an input of a digital circuit device including a capacitive node. The method also includes selectively activating a voltage level adjustment element to regulate an electrical discharge path from the capacitive node to an electrical ground to prevent complete discharge of the capacitive node. In a particular illustrative embodiment, the received signal may be a clock signal.
摘要翻译： 在具体说明性实施例中，公开了电路装置和控制电压摆幅的方法。 该方法包括在包括电容性节点的数字电路装置的输入处接收信号。 该方法还包括选择性地激活电压电平调节元件以调节从电容节点到电接地的放电路径，以防止电容性节点的完全放电。 在特定说明性实施例中，接收信号可以是时钟信号。
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公开(公告)号：US20070300108A1
公开(公告)日：2007-12-27
申请号：US11473219
申请日：2006-06-22
申请人： Martin Saint-Laurent , Paul Bassett , Prayag Patel
发明人： Martin Saint-Laurent , Paul Bassett , Prayag Patel
IPC分类号： G01R31/28
CPC分类号： G01R31/318552 , G01R31/3025 , G01R31/318575
摘要： A logic device includes a data input, a scan test input, a clock demultiplexer, and a master latch. The clock demultiplexer is responsive to a clock input to selectively provide a first clock output and a second clock output. The master latch is coupled to the data input and to the scan test input and includes an output. The master latch is responsive to the first clock output of the clock demultiplexer and the second clock output of the clock demultiplexer to selectively couple the data input or the scan test input to the output.
摘要翻译： 逻辑器件包括数据输入，扫描测试输入，时钟解复用器和主锁存器。 时钟解复用器响应于时钟输入以选择性地提供第一时钟输出和第二时钟输出。 主锁存器耦合到数据输入和扫描测试输入，并包括输出。 主锁存器响应于时钟解复用器的第一时钟输出和时钟解复用器的第二时钟输出，以选择性地将数据输入或扫描测试输入耦合到输出。
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