A continuous-time sigma-delta analog to digital converter (CTSD ADC) includes a comparator that samples the time integral of an analog signal at each rising edge and falling edge of a sampling clock. A feedback block, operating as a digital to analog converter, receives the outputs of the comparator and generates corresponding analog signals also at each rising and falling edge of the sampling clock. The feedback blocks are implemented as either switched-resistor or switched-current circuits. High signal-to-noise ratio (SNR) is achieved in the CTSD ADC without the need to use very high sampling clock frequencies. Compensation for excess loop delay is provided using a local feedback technique. In an embodiment, the sigma delta modulator in the CTSD ADC is implemented as a second order loop, and the comparator as a two-level comparator.