公开(公告)号：US08400340B2

公开(公告)日：2013-03-19

申请号：US13184570

申请日：2011-07-18

申请人： Vineet Mishra ,  Jayawardan Janardhanan ,  Samala Sreekiran ,  Meghna Agrawal

发明人： Vineet Mishra ,  Jayawardan Janardhanan ,  Samala Sreekiran ,  Meghna Agrawal

IPC分类号： H03M3/00

CPC分类号： H03M3/496 ,  H03M3/39 ,  H03M3/464

摘要： A continuous-time sigma-delta analog to digital converter (CTSD ADC) includes a comparator that samples the time integral of an analog signal at each rising edge and falling edge of a sampling clock. A feedback block, operating as a digital to analog converter, receives the outputs of the comparator and generates corresponding analog signals also at each rising and falling edge of the sampling clock. The feedback blocks are implemented as either switched-resistor or switched-current circuits. High signal-to-noise ratio (SNR) is achieved in the CTSD ADC without the need to use very high sampling clock frequencies. Compensation for excess loop delay is provided using a local feedback technique. In an embodiment, the sigma delta modulator in the CTSD ADC is implemented as a second order loop, and the comparator as a two-level comparator.

摘要翻译： 连续时间Σ-Δ模数转换器（CTSD ADC）包括在采样时钟的每个上升沿和下降沿采样模拟信号的时间积分的比较器。 作为数模转换器工作的反馈块接收比较器的输出，并在采样时钟的每个上升沿和下降沿也产生相应的模拟信号。 反馈块实现为开关电阻或开关电流电路。 在CTSD ADC中实现了高信噪比（SNR），而不需要使用非常高的采样时钟频率。 使用本地反馈技术提供多余回路延迟的补偿。 在一个实施例中，CTSD ADC中的Σ-Δ调制器被实现为二阶环路，比较器被实现为两电平比较器。

公开(公告)号：US20110283014A1

公开(公告)日：2011-11-17

申请号：US12780120

申请日：2010-05-14

申请人： Rahul Malik ,  Meghna Agrawal

发明人： Rahul Malik ,  Meghna Agrawal

IPC分类号： G06F15/16

CPC分类号： H04L47/10

摘要： Performing transmission of data over network using at least a first and second rate adaptation algorithm. The transmission of data may use a plurality of buffers. It may be determined that a number of available buffers of the plurality of buffers is below a first threshold. Accordingly, data may be transmitted according to the second rate adaptation algorithm which provides increased flowrate. During the transmission of the data, it may be determined that the number of available buffers of the plurality of buffers exceeds a second threshold. Accordingly, data may be transmitted according to the first rate adaptation algorithm that provides increased throughput.

摘要翻译： 使用至少第一和第二速率自适应算法执行网络上的数据传输。 数据的传输可以使用多个缓冲器。 可以确定多个缓冲器中的多个可用缓冲器低于第一阈值。 因此，可以根据提供增加的流量的第二速率自适应算法来发送数据。 在传输数据期间，可以确定多个缓冲器中的可用缓冲器的数量超过第二阈值。 因此，可以根据提供增加的吞吐量的第一速率自适应算法来发送数据。

公开(公告)号：US20130021182A1

公开(公告)日：2013-01-24

申请号：US13184570

申请日：2011-07-18

申请人： Vineet Mishra ,  Jayawardan Janardhanan ,  Samala Sreekiran ,  Meghna Agrawal

发明人： Vineet Mishra ,  Jayawardan Janardhanan ,  Samala Sreekiran ,  Meghna Agrawal

IPC分类号： H03M3/02

CPC分类号： H03M3/496 ,  H03M3/39 ,  H03M3/464

摘要： A continuous-time sigma-delta analog to digital converter (CTSD ADC) includes a comparator that samples the time integral of an analog signal at each rising edge and falling edge of a sampling clock. A feedback block, operating as a digital to analog converter, receives the outputs of the comparator and generates corresponding analog signals also at each rising and falling edge of the sampling clock. The feedback blocks are implemented as either switched-resistor or switched-current circuits. High signal-to-noise ratio (SNR) is achieved in the CTSD ADC without the need to use very high sampling clock frequencies. Compensation for excess loop delay is provided using a local feedback technique. In an embodiment, the sigma delta modulator in the CTSD ADC is implemented as a second order loop, and the comparator as a two-level comparator.

摘要翻译： 连续时间Σ-Δ模数转换器（CTSD ADC）包括在采样时钟的每个上升沿和下降沿采样模拟信号的时间积分的比较器。 作为数模转换器工作的反馈块接收比较器的输出，并在采样时钟的每个上升沿和下降沿也产生相应的模拟信号。 反馈块实现为开关电阻或开关电流电路。 在CTSD ADC中实现了高信噪比（SNR），而不需要使用非常高的采样时钟频率。 使用本地反馈技术提供多余回路延迟的补偿。 在一个实施例中，CTSD ADC中的Σ-Δ调制器被实现为二阶环路，比较器被实现为两电平比较器。