Invention Grant
US08405164B2 Tri-gate transistor device with stress incorporation layer and method of fabrication
有权
具有应力结合层的三栅晶体管器件及其制造方法
- Patent Title: Tri-gate transistor device with stress incorporation layer and method of fabrication
- Patent Title (中): 具有应力结合层的三栅晶体管器件及其制造方法
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Application No.: US12767681Application Date: 2010-04-26
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Publication No.: US08405164B2Publication Date: 2013-03-26
- Inventor: Scott A. Hareland , Robert S. Chau , Brian S. Doyle , Suman Datta , Been-Yih Jin
- Applicant: Scott A. Hareland , Robert S. Chau , Brian S. Doyle , Suman Datta , Been-Yih Jin
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: H01L29/06
- IPC: H01L29/06
Abstract:
A semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls is formed on an insulating substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and is formed adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. A thin film is then formed adjacent to the semiconductor body wherein the thin film produces a stress in the semiconductor body.
Public/Granted literature
- US20100200917A1 NONPLANAR DEVICE WITH STRESS INCORPORATION LAYER AND METHOD OF FABRICATION Public/Granted day:2010-08-12
Information query
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