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    Short circuit fault-tolerance in an implantable medical device
    1.
    发明授权
    Short circuit fault-tolerance in an implantable medical device 有权
    可植入医疗器械的短路容错

    公开(公告)号：US08626287B2

    公开(公告)日：2014-01-07

    申请号：US13221617

    申请日：2011-08-30

    申请人： Scott A. Hareland

    发明人： Scott A. Hareland

    IPC分类号： A61N1/39

    CPC分类号： A61N1/3918 ,  A61N1/3931 ,  A61N1/3956

    摘要： A device includes an energy storage device, a plurality of electrodes, a memory, a switching circuit, and a processing module. The energy storage device stores electrical energy for delivery of defibrillation therapy to a heart. The memory stores N therapy configurations that define which of the plurality of electrodes are used to deliver defibrillation therapy and a waveform to be applied during delivery of defibrillation therapy. The switching circuit connects the plurality of electrodes to the energy storage device. The processing module controls the switching circuit to deliver defibrillation therapy according to a first therapy configuration of the N therapy configurations, detects a short circuit fault during delivery of the defibrillation therapy according to the first therapy configuration, and selects a second therapy configuration of the N therapy configurations based on when the short circuit fault was detected during delivery of the defibrillation therapy according to the first therapy configuration.

    摘要翻译： 一种装置包括能量存储装置，多个电极，存储器，开关电路和处理模块。 能量存储装置存储用于向心脏递送除颤疗法的电能。 存储器存储N种治疗配置，其限定多个电极中的哪一个用于递送除颤疗法和在除颤治疗递送期间施加的波形。 开关电路将多个电极连接到能量存储装置。 所述处理模块根据所述N种治疗方式的第一治疗结构，控制所述切换电路进行除颤治疗，根据所述第一治疗结构检测所述除颤疗法的输送期间的短路故障，并选择所述N次 基于根据第一治疗配置在除颤治疗递送期间检测到短路故障的治疗配置。

    Method of fabricating a robust gate dielectric using a replacement gate flow
    4.
    发明授权
    Method of fabricating a robust gate dielectric using a replacement gate flow 失效
    使用更换栅流制造坚固的栅极电介质的方法

    公开(公告)号：US07078750B2

    公开(公告)日：2006-07-18

    申请号：US11026066

    申请日：2004-12-30

    申请人： Scott A. Hareland ,  Mark L. Doczy ,  Robert S. Chau

    发明人： Scott A. Hareland ,  Mark L. Doczy ,  Robert S. Chau

    IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC分类号： H01L21/28185 ,  H01L21/26586 ,  H01L21/28194 ,  H01L21/28202 ,  H01L29/512 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

    摘要： A method is described for selectively treating the properties of a gate dielectric near corners of the gate without altering the gate dielectric in a center region of a gate channel. The method includes providing a structure having a gate opening and depositing a layer of dielectric with a high dielectric constant on a bottom surface and side walls of the gate opening. The corner regions of the high dielectric constant layer formed adjacent to the bottom surface and the side walls of the gate opening are selectively treated without altering the center region of the high dielectric constant layer formed at the bottom surface of the gate opening.

    摘要翻译： 描述了一种方法，用于选择性地处理在栅极角附近的栅极电介质的性质，而不改变栅极沟道的中心区域中的栅极电介质。 该方法包括提供具有栅极开口并且在栅极开口的底表面和侧壁上沉积具有高介电常数的电介质层的结构。 选择性地处理邻近底表面和栅极开口形成的高介电常数层的角区域，而不改变形成在栅极开口底表面处的高介电常数层的中心区域。

    Fault-tolerant high voltage delivery in an implantable medical device
    5.
    发明授权
    Fault-tolerant high voltage delivery in an implantable medical device 有权
    可植入医疗设备中的容错高压输送

    公开(公告)号：US08467872B2

    公开(公告)日：2013-06-18

    申请号：US13221558

    申请日：2011-08-30

    申请人： Scott A. Hareland

    发明人： Scott A. Hareland

    IPC分类号： A61N1/00

    CPC分类号： A61N1/3937 ,  A61N1/3918 ,  A61N1/3925 ,  A61N2001/083

    摘要： A medical device includes an energy storage device, a plurality of electrodes, a memory, a switching circuit, and a processing module. The energy storage device stores electrical energy for delivery of defibrillation therapy to a heart. The memory stores N therapy configurations, each of the N therapy configurations defining which of the plurality of electrodes are used to deliver defibrillation therapy and further defining a waveform to be applied during delivery of defibrillation therapy. The switching circuit is configured to connect the plurality of electrodes to the energy storage device. The processing module is configured to control the switching circuit to deliver defibrillation therapy according to a first therapy configuration, detect a fault during delivery of the defibrillation therapy according to the first therapy configuration, and select a second therapy configuration based on when the fault was detected during delivery of the defibrillation therapy according to the first therapy configuration.

    摘要翻译： 医疗装置包括能量存储装置，多个电极，存储器，开关电路和处理模块。 能量存储装置存储用于向心脏递送除颤疗法的电能。 存储器存储N个治疗配置，N个治疗配置中的每个配置限定多个电极中的哪一个用于递送除颤治疗，并进一步限定在递送除颤治疗期间应用的波形。 开关电路被配置为将多个电极连接到能量存储装置。 处理模块被配置为根据第一治疗配置来控制切换电路进行除颤治疗，根据第一治疗配置检测除颤治疗期间的故障，并且基于检测到故障时选择第二治疗配置 在根据第一疗法配置的除颤疗法递送期间。

    FAULT-TOLERANT SENSING IN AN IMPLANTABLE MEDICAL DEVICE
    6.
    发明申请
    FAULT-TOLERANT SENSING IN AN IMPLANTABLE MEDICAL DEVICE 审中-公开
    在可植入医疗器械中的容错感测

    公开(公告)号：US20130109985A1

    公开(公告)日：2013-05-02

    申请号：US13285872

    申请日：2011-10-31

    申请人： Jeffrey M. Gillberg ,  Scott A. Hareland ,  Leonard P. Radtke ,  David G. Schaenzer ,  John D. Wahlstrand

    发明人： Jeffrey M. Gillberg ,  Scott A. Hareland ,  Leonard P. Radtke ,  David G. Schaenzer ,  John D. Wahlstrand

    IPC分类号： A61B5/0402

    CPC分类号： A61B5/7221 ,  A61B5/0464 ,  A61B5/7203 ,  A61B2560/0266

    摘要： A system includes a memory and a processing module. The memory includes a primary sensing vector and N alternate sensing vectors. The processing module determines a ranking value for each of the N alternate sensing vectors. Each ranking value is indicative of the integrity of a cardiac electrical signal acquired via the corresponding alternate sensing vector. The processing module senses cardiac events using the primary sensing vector, detects a reduction in the integrity of a cardiac electrical signal acquired via the primary sensing vector, and selects one of the N alternate sensing vectors in response to detecting a reduction in the integrity of the cardiac electrical signal acquired via the primary sensing vector. The selection is based on the ranking value associated with the one of the N alternate sensing vectors. The processing module then senses cardiac events using the selected one of the N alternate sensing vectors.

    摘要翻译： 系统包括存储器和处理模块。 存储器包括主感测矢量和N个备选感测矢量。 处理模块确定N个备选感测向量中的每一个的排序值。 每个排序值表示通过相应的替代感测矢量获取的心脏电信号的完整性。 处理模块使用主感测向量感测心脏事件，检测通过主感测向量获取的心电信号的完整性的降低，并且响应于检测到所述N个备选感测向量的完整性的降低而选择N个备选感测向量中的一个 通过主感测矢量获得的心电信号。 选择是基于与N个备选感测向量之一相关联的排名值。 处理模块然后使用所选择的N个备选感测向量之一来感测心脏事件。

    SHORT CIRCUIT FAULT-TOLERANCE IN AN IMPLANTABLE MEDICAL DEVICE
    8.
    发明申请
    SHORT CIRCUIT FAULT-TOLERANCE IN AN IMPLANTABLE MEDICAL DEVICE 有权
    短路电路在可移植医疗设备中的容错性

    公开(公告)号：US20130053911A1

    公开(公告)日：2013-02-28

    申请号：US13221617

    申请日：2011-08-30

    申请人： Scott A. Hareland

    发明人： Scott A. Hareland

    IPC分类号： A61N1/39

    CPC分类号： A61N1/3918 ,  A61N1/3931 ,  A61N1/3956

    摘要： A device includes an energy storage device, a plurality of electrodes, a memory, a switching circuit, and a processing module. The energy storage device stores electrical energy for delivery of defibrillation therapy to a heart. The memory stores N therapy configurations that define which of the plurality of electrodes are used to deliver defibrillation therapy and a waveform to be applied during delivery of defibrillation therapy. The switching circuit connects the plurality of electrodes to the energy storage device. The processing module controls the switching circuit to deliver defibrillation therapy according to a first therapy configuration of the N therapy configurations, detects a short circuit fault during delivery of the defibrillation therapy according to the first therapy configuration, and selects a second therapy configuration of the N therapy configurations based on when the short circuit fault was detected during delivery of the defibrillation therapy according to the first therapy configuration.

    摘要翻译： 一种装置包括能量存储装置，多个电极，存储器，开关电路和处理模块。 能量存储装置存储用于向心脏递送除颤疗法的电能。 存储器存储N种治疗配置，其限定多个电极中的哪一个用于递送除颤疗法和在除颤治疗递送期间施加的波形。 开关电路将多个电极连接到能量存储装置。 所述处理模块根据所述N种治疗方式的第一治疗结构，控制所述切换电路进行除颤治疗，根据所述第一治疗结构检测所述除颤疗法的输送期间的短路故障，并选择所述N次 基于根据第一治疗配置在除颤治疗递送期间检测到短路故障的治疗配置。

    NONPLANAR SEMICONDUCTOR DEVICE WITH PARTIALLY OR FULLY WRAPPED AROUND GATE ELECTRODE AND METHODS OF FABRICATION
    9.
    发明申请
    NONPLANAR SEMICONDUCTOR DEVICE WITH PARTIALLY OR FULLY WRAPPED AROUND GATE ELECTRODE AND METHODS OF FABRICATION 有权
    非门式半导体器件，部分或完全包裹在门电极和制造方法

    公开(公告)号：US20110020987A1

    公开(公告)日：2011-01-27

    申请号：US12893753

    申请日：2010-09-29

    申请人： Scott A. Hareland ,  Robert S. Chau ,  Brian S. Doyle ,  Rafael Rios ,  Tom Linton ,  Suman Datta

    发明人： Scott A. Hareland ,  Robert S. Chau ,  Brian S. Doyle ,  Rafael Rios ,  Tom Linton ,  Suman Datta

    IPC分类号： H01L21/336 ,  H01L21/762

    CPC分类号： H01L29/785 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/66795

    摘要： A nonplanar semiconductor device and its method of fabrication is described. The nonplanar semiconductor device includes a semiconductor body having a top surface opposite a bottom surface formed above an insulating substrate wherein the semiconductor body has a pair laterally opposite sidewalls. A gate dielectric is formed on the top surface of the semiconductor body on the laterally opposite sidewalls of the semiconductor body and on at least a portion of the bottom surface of semiconductor body. A gate electrode is formed on the gate dielectric, on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of semiconductor body and beneath the gate dielectric on the bottom surface of the semiconductor body. A pair source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.

    摘要翻译： 描述了非平面半导体器件及其制造方法。 非平面半导体器件包括半导体本体，该半导体本体具有与形成在绝缘基板上方的底表面相对的顶表面，其中半导体本体具有一对横向相对的侧壁。 在半导体本体的横向相对的侧壁和半导体本体的底表面的至少一部分上的半导体本体的顶表面上形成栅极电介质。 栅极电极形成在半导体本体的顶表面上并与半导体本体的横向相对的侧壁上的栅电介质相邻并位于半导体本体的底表面上的栅电介质之下的栅电介质上。 在栅电极的相对侧的半导体本体中形成一对源/漏区。

    NONPLANAR SEMICONDUCTOR DEVICE WITH PARTIALLY OR FULLY WRAPPED AROUND GATE ELECTRODE AND METHODS OF FABRICATION
    10.
    发明申请
    NONPLANAR SEMICONDUCTOR DEVICE WITH PARTIALLY OR FULLY WRAPPED AROUND GATE ELECTRODE AND METHODS OF FABRICATION 有权
    非门式半导体器件，部分或完全包裹在门电极和制造方法

    公开(公告)号：US20090061572A1

    公开(公告)日：2009-03-05

    申请号：US12259464

    申请日：2008-10-28

    申请人： Scott A. Hareland ,  Robert S. Chau ,  Brian S. Doyle ,  Rafael Rios ,  Tom Linton ,  Suman Datta

    发明人： Scott A. Hareland ,  Robert S. Chau ,  Brian S. Doyle ,  Rafael Rios ,  Tom Linton ,  Suman Datta

    IPC分类号： H01L21/336

    CPC分类号： H01L29/785 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/66795

    摘要： A nonplanar semiconductor device and its method of fabrication is described. The nonplanar semiconductor device includes a semiconductor body having a top surface opposite a bottom surface formed above an insulating substrate wherein the semiconductor body has a pair laterally opposite sidewalls. A gate dielectric is formed on the top surface of the semiconductor body on the laterally opposite sidewalls of the semiconductor body and on at least a portion of the bottom surface of semiconductor body. A gate electrode is formed on the gate dielectric, on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of semiconductor body and beneath the gate dielectric on the bottom surface of the semiconductor body. A pair source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.

    摘要翻译： 描述了非平面半导体器件及其制造方法。 非平面半导体器件包括半导体本体，该半导体本体具有与形成在绝缘基板上方的底表面相对的顶表面，其中半导体本体具有一对横向相对的侧壁。 在半导体本体的横向相对的侧壁和半导体本体的底表面的至少一部分上的半导体本体的顶表面上形成栅极电介质。 栅极电极形成在半导体本体的顶表面上并与半导体本体的横向相对的侧壁上的栅电介质相邻并位于半导体本体的底表面上的栅电介质之下的栅电介质上。 在栅电极的相对侧的半导体本体中形成一对源/漏区。