发明授权
US08405432B2 Output buffer circuit, input buffer circuit, and input/output buffer circuit
有权
输出缓冲电路,输入缓冲电路,输入/输出缓冲电路
- 专利标题: Output buffer circuit, input buffer circuit, and input/output buffer circuit
- 专利标题(中): 输出缓冲电路,输入缓冲电路,输入/输出缓冲电路
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申请号: US12963114申请日: 2010-12-08
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公开(公告)号: US08405432B2公开(公告)日: 2013-03-26
- 发明人: Masaru Koyanagi , Yasufumi Kajiyama , Ryo Fukuda , Fumiyoshi Matsuoka , Yasuhiro Suematsu
- 申请人: Masaru Koyanagi , Yasufumi Kajiyama , Ryo Fukuda , Fumiyoshi Matsuoka , Yasuhiro Suematsu
- 申请人地址: JP Tokyo
- 专利权人: Kabushiki Kaisha Toshiba
- 当前专利权人: Kabushiki Kaisha Toshiba
- 当前专利权人地址: JP Tokyo
- 代理机构: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- 优先权: JP2009-279267 20091209
- 主分类号: H03K3/01
- IPC分类号: H03K3/01
摘要:
An output buffer circuit in accordance with an embodiment comprises a plurality of buffer circuits, each of the buffer circuits including a transistor operative to change an output signal of an output terminal in response to a change in an input signal, the output buffer circuit being configured to enable the plurality of buffer circuits to be driven selectively. Each of the plurality of buffer circuits includes a plurality of output transistors having respective current paths formed in parallel to one another between a fixed voltage terminal supplying a certain fixed voltage and an output terminal, and being selectively rendered in an operable state in accordance with a control signal provided from external. The plurality of output transistors included in each of the plurality of buffer circuits are formed having a certain size ratio.
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