公开(公告)号：US08405432B2

公开(公告)日：2013-03-26

申请号：US12963114

申请日：2010-12-08

申请人： Masaru Koyanagi ,  Yasufumi Kajiyama ,  Ryo Fukuda ,  Fumiyoshi Matsuoka ,  Yasuhiro Suematsu

发明人： Masaru Koyanagi ,  Yasufumi Kajiyama ,  Ryo Fukuda ,  Fumiyoshi Matsuoka ,  Yasuhiro Suematsu

IPC分类号： H03K3/01

CPC分类号： H03K19/00384 ,  H03K19/01721

摘要： An output buffer circuit in accordance with an embodiment comprises a plurality of buffer circuits, each of the buffer circuits including a transistor operative to change an output signal of an output terminal in response to a change in an input signal, the output buffer circuit being configured to enable the plurality of buffer circuits to be driven selectively. Each of the plurality of buffer circuits includes a plurality of output transistors having respective current paths formed in parallel to one another between a fixed voltage terminal supplying a certain fixed voltage and an output terminal, and being selectively rendered in an operable state in accordance with a control signal provided from external. The plurality of output transistors included in each of the plurality of buffer circuits are formed having a certain size ratio.

摘要翻译： 根据实施例的输出缓冲器电路包括多个缓冲电路，每个缓冲电路包括一个晶体管，用于响应于输入信号的变化而改变输出端的输出信号，该输出缓冲电路被配置 以使得能够选择性地驱动多个缓冲电路。 多个缓冲电路中的每一个包括多个输出晶体管，其具有在提供一定固定电压的固定电压端子和输出端子之间彼此并联形成的各自的电流路径，并且根据 控制信号由外部提供。 包含在多个缓冲电路的每一个中的多个输出晶体管形成为具有一定的尺寸比。

公开(公告)号：US20110133791A1

公开(公告)日：2011-06-09

申请号：US12963114

申请日：2010-12-08

申请人： Masaru Koyanagi ,  Yasufumi Kajiyama ,  Ryo Fukuda ,  Fumiyoshi Matsuoka ,  Yasuhiro Suematsu

发明人： Masaru Koyanagi ,  Yasufumi Kajiyama ,  Ryo Fukuda ,  Fumiyoshi Matsuoka ,  Yasuhiro Suematsu

IPC分类号： H03K3/01

CPC分类号： H03K19/00384 ,  H03K19/01721

摘要： An output buffer circuit in accordance with an embodiment comprises a plurality of buffer circuits, each of the buffer circuits including a transistor operative to change an output signal of an output terminal in response to a change in an input signal, the output buffer circuit being configured to enable the plurality of buffer circuits to be driven selectively. Each of the plurality of buffer circuits includes a plurality of output transistors having respective current paths formed in parallel to one another between a fixed voltage terminal supplying a certain fixed voltage and an output terminal, and being selectively rendered in an operable state in accordance with a control signal provided from external. The plurality of output transistors included in each of the plurality of buffer circuits are formed having a certain size ratio.

摘要翻译： 根据实施例的输出缓冲器电路包括多个缓冲电路，每个缓冲电路包括一个晶体管，用于响应于输入信号的变化而改变输出端的输出信号，该输出缓冲电路被配置 以使得能够选择性地驱动多个缓冲电路。 多个缓冲电路中的每一个包括多个输出晶体管，其具有在提供一定固定电压的固定电压端子和输出端子之间彼此并联形成的各自的电流路径，并且根据 控制信号由外部提供。 包含在多个缓冲电路的每一个中的多个输出晶体管形成为具有一定的尺寸比。

公开(公告)号：US20110148211A1

公开(公告)日：2011-06-23

申请号：US12885935

申请日：2010-09-20

申请人： Fumiyoshi MATSUOKA ,  Ryo Fukuda

发明人： Fumiyoshi MATSUOKA ,  Ryo Fukuda

IPC分类号： H02J4/00

CPC分类号： H02M3/157 ,  Y10T307/696

摘要： In a semiconductor device according to the embodiment, a core circuit is an IC. A peripheral circuit includes a driver supplied with voltages from an internal power source and an external power source and outputting data transferred from the core circuit, and a fetch portion transferring the digital data to the driver. A first power source supplies an internal voltage to the driver via a power source line. A second power source includes current driving strings each including a current driving element and a switching element connected in series between the external power source and the power source line. The second power source supplies a current to the power source line separately from the first power source line by driving the current driving strings. A power source controller controls the second power source to drive the current driving strings when a logic transition occurs among consecutive bits of the data.

摘要翻译： 在根据实施例的半导体器件中，核心电路是IC。 外围电路包括从内部电源和外部电源提供电压的驱动器，并输出从核心电路传送的数据，以及将数字数据传送给驱动器的取出部分。 第一电源通过电源线向驱动器提供内部电压。 第二电源包括各自包括串联连接在外部电源和电源线之间的电流驱动元件和开关元件的电流驱动串。 第二电源通过驱动当前驱动串来将电流与第一电源线分开地提供给电源线。 当在数据的连续位之间发生逻辑转换时，电源控制器控制第二电源来驱动当前驱动串。

公开(公告)号：US07732840B2

公开(公告)日：2010-06-08

申请号：US11864041

申请日：2007-09-28

申请人： Fumiyoshi Matsuoka ,  Yohji Watanabe ,  Ryo Fukuda

发明人： Fumiyoshi Matsuoka ,  Yohji Watanabe ,  Ryo Fukuda

IPC分类号： H01L21/76

CPC分类号： H03K3/356191 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1104

摘要： A second-conductivity-type transistor includes a source and drain formed by a second-conductivity-type diffusion layer formed on a first-conductivity-type semiconductor layer; and a gate formed on the first-conductivity-type semiconductor layer sandwiched between the second-conductivity-type diffusion layer through an insulating film A first-conductivity-type transistor includes a source and drain formed by a first-conductivity-type diffusion layer formed on a second-conductivity-type semiconductor layer; and a gate formed on the second-conductivity-type semiconductor layer sandwiched between the first-conductivity-type diffusion layer through an insulating film. The second-conductivity-type diffusion layer for configuring the second-conductivity-type transistor is divided into a plurality of regions, each of which being separated by a device isolation region formed on the first-conductivity-type semiconductor layer. The first-conductivity-type diffusion layer for configuring the first-conductivity-type transistor is divided into a plurality of regions, each of which being separated by a device isolation region formed on the second-conductivity-type semiconductor layer.

摘要翻译： 第二导电型晶体管包括由形成在第一导电型半导体层上的第二导电型扩散层形成的源极和漏极; 并且通过绝缘膜夹在第二导电型扩散层之间的第一导电型半导体层上形成的栅极第一导电型晶体管包括由形成的第一导电型扩散层形成的源极和漏极 在第二导电型半导体层上; 以及形成在通过绝缘膜夹在第一导电型扩散层之间的第二导电型半导体层上的栅极。 用于构造第二导电型晶体管的第二导电型扩散层被分成多个区域，每个区域被形成在第一导电型半导体层上的器件隔离区分隔开。 用于构造第一导电型晶体管的第一导电型扩散层被分成多个区域，每个区域被形成在第二导电类型半导体层上的器件隔离区隔开。

公开(公告)号：US20080079473A1

公开(公告)日：2008-04-03

申请号：US11864041

申请日：2007-09-28

申请人： Fumiyoshi Matsuoka ,  Yohji Watanabe ,  Ryo Fukuda

发明人： Fumiyoshi Matsuoka ,  Yohji Watanabe ,  Ryo Fukuda

IPC分类号： H03K3/356

CPC分类号： H03K3/356191 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1104

摘要： A second-conductivity-type transistor includes a source and drain formed by a second-conductivity-type diffusion layer formed on a first-conductivity-type semiconductor layer; and a gate formed on the first-conductivity-type semiconductor layer sandwiched between the second-conductivity-type diffusion layer through an insulating film A first-conductivity-type transistor includes a source and drain formed by a first-conductivity-type diffusion layer formed on a second-conductivity-type semiconductor layer; and a gate formed on the second-conductivity-type semiconductor layer sandwiched between the first-conductivity-type diffusion layer through an insulating film. The second-conductivity-type diffusion layer for configuring the second-conductivity-type transistor is divided into a plurality of regions, each of which being separated by a device isolation region formed on the first-conductivity-type semiconductor layer. The first-conductivity-type diffusion layer for configuring the first-conductivity-type transistor is divided into a plurality of regions, each of which being separated by a device isolation region formed on the second-conductivity-type semiconductor layer.

摘要翻译： 第二导电型晶体管包括由形成在第一导电型半导体层上的第二导电型扩散层形成的源极和漏极; 并且通过绝缘膜夹在第二导电型扩散层之间的第一导电型半导体层上形成的栅极第一导电型晶体管包括由形成的第一导电型扩散层形成的源极和漏极 在第二导电型半导体层上; 以及形成在通过绝缘膜夹在第一导电型扩散层之间的第二导电型半导体层上的栅极。 用于构造第二导电型晶体管的第二导电型扩散层被分成多个区域，每个区域被形成在第一导电型半导体层上的器件隔离区分隔开。 用于构造第一导电型晶体管的第一导电型扩散层被分成多个区域，每个区域被形成在第二导电类型半导体层上的器件隔离区隔开。

公开(公告)号：US20110128063A1

公开(公告)日：2011-06-02

申请号：US12884533

申请日：2010-09-17

申请人： Ryo Fukuda ,  Masaru Koyanagi

发明人： Ryo Fukuda ,  Masaru Koyanagi

IPC分类号： H03L5/00

CPC分类号： H03K3/356113

摘要： According to one embodiment, a semiconductor integrated circuit includes first and second level shift circuits. The first level shifter includes a plurality of transistors and is connected to a power source voltage supply node of a first power source system and to which a first signal of a second power source system and a level inversion signal of the first signal are input. The second level shifter includes a plurality of transistors and is connected to the power source voltage supply node of the first power source system and to which the level inversion signal of the first signal of the second power source system and an output signal of the first level shifter are input. The first and second level shifters have substantially the same circuit configuration and driving abilities of corresponding ones of the transistors in the first and second level shifters are substantially set equal.

摘要翻译： 根据一个实施例，半导体集成电路包括第一和第二电平移位电路。 第一电平移位器包括多个晶体管，并连接到第一电源系统的电源电压供应节点，第二电源系统的第一信号和第一信号的电平反转信号被输入到该第一电源系统。 第二电平移位器包括多个晶体管，并连接到第一电源系统的电源电压供应节点，并且第二电源系统的第一信号的电平反转信号和第一电平系统的输出信号 移位器被输入。 第一和第二电平移位器具有基本上相同的电路配置，并且第一和第二电平移位器中对应的晶体管的驱动能力基本上相等。

公开(公告)号：US08258817B2

公开(公告)日：2012-09-04

申请号：US12884623

申请日：2010-09-17

申请人： Ryo Fukuda ,  Masaru Koyanagi

发明人： Ryo Fukuda ,  Masaru Koyanagi

IPC分类号： H03K5/153

CPC分类号： H01L27/092 ,  H01L2924/0002 ,  H03F3/3028 ,  H03F3/45183 ,  H03F2200/411 ,  H03F2203/45511 ,  H01L2924/00

摘要： According to one embodiment, a semiconductor integrated circuit includes first to six transistors and a constant current source circuit. The first and second transistors form a current mirror circuit connected to a first power source node. The third and fourth transistors form a differential pair circuit. The third and fourth transistors receive first and second external signals at their gates, respectively. The constant current source circuit has one end connected to source terminals of the third and fourth transistors, and the other end connected to a second power source node. The fifth and sixth transistors form a current pathway between a common gate node of the first and second transistors and the constant current source circuit. The gate of fifth transistor is connected to a signal output node. The gate of sixth transistor receives a signal of logic opposite to a signal to be obtained at the signal output node.

摘要翻译： 根据一个实施例，半导体集成电路包括第一至六个晶体管和恒流源电路。 第一和第二晶体管形成连接到第一电源节点的电流镜电路。 第三和第四晶体管形成差分对电路。 第三和第四晶体管分别在其栅极处接收第一和第二外部信号。 恒流源电路的一端连接到第三和第四晶体管的源极端子，另一端连接到第二电源节点。 第五和第六晶体管在第一和第二晶体管的公共栅极节点与恒流源电路之间形成电流通路。 第五晶体管的栅极连接到信号输出节点。 第六晶体管的栅极接收与在信号输出节点处获得的信号相反的逻辑信号。

公开(公告)号：US08558602B2

公开(公告)日：2013-10-15

申请号：US12884533

申请日：2010-09-17

申请人： Ryo Fukuda ,  Masaru Koyanagi

发明人： Ryo Fukuda ,  Masaru Koyanagi

IPC分类号： H03L5/00

CPC分类号： H03K3/356113

摘要： According to one embodiment, a semiconductor integrated circuit includes first and second level shift circuits. The first level shifter includes a plurality of transistors and is connected to a power source voltage supply node of a first power source system and to which a first signal of a second power source system and a level inversion signal of the first signal are input. The second level shifter includes a plurality of transistors and is connected to the power source voltage supply node of the first power source system and to which the level inversion signal of the first signal of the second power source system and an output signal of the first level shifter are input. The first and second level shifters have substantially the same circuit configuration and driving abilities of corresponding ones of the transistors in the first and second level shifters are substantially set equal.

摘要翻译： 根据一个实施例，半导体集成电路包括第一和第二电平移位电路。 第一电平移位器包括多个晶体管，并连接到第一电源系统的电源电压供应节点，第二电源系统的第一信号和第一信号的电平反转信号被输入到该第一电源系统。 第二电平移位器包括多个晶体管，并连接到第一电源系统的电源电压供应节点，并且第二电源系统的第一信号的电平反转信号和第一电平系统的输出信号 移位器被输入。 第一和第二电平移位器具有基本上相同的电路配置，并且第一和第二电平移位器中对应的晶体管的驱动能力基本上相等。

公开(公告)号：US08405428B2

公开(公告)日：2013-03-26

申请号：US13098752

申请日：2011-05-02

申请人： Ryo Fukuda ,  Masaru Koyanagi

发明人： Ryo Fukuda ,  Masaru Koyanagi

IPC分类号： H03K5/153

CPC分类号： H03K17/04 ,  H03K19/018521

摘要： A constant current source circuit includes one end connected to a second node as sources of third and fourth transistors, and the other end connected to a second power supply node that supplies a second voltage different from a first voltage. The clamp circuit is configured to form a current path between the second node and the second power supply node. It adjusts the potential of the second node to a certain potential when a first external input signal is switched from a first state to a second state.

摘要翻译： 恒流源电路包括连接到第二节点的一端作为第三和第四晶体管的源极，另一端连接到提供不同于第一电压的第二电压的第二电源节点。 钳位电路被配置为在第二节点和第二电源节点之间形成电流路径。 当第一外部输入信号从第一状态切换到第二状态时，它将第二节点的电位调整到一定的电位。

公开(公告)号：US20120068256A1

公开(公告)日：2012-03-22

申请号：US13232492

申请日：2011-09-14

申请人： Ryo Fukuda ,  Yoshihisa Iwata

发明人： Ryo Fukuda ,  Yoshihisa Iwata

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L27/11578 ,  G11C16/0416 ,  H01L27/11565 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

摘要： An dielectric film is formed above the semiconductor substrate. A first conductive layer is formed in the dielectric film and extending in a first direction. The first conductive layer is connected to a first select transistor. A second conductive layer formed in the dielectric film and extending in the first direction. The second conductive layer is connected to a second select transistor. A semiconductor layer is connected to both the first and second conductive layers and functioning as a channel layer of a memory transistor. A gate-insulating film is formed on the semiconductor layer. The gate-insulating film includes a charge accumulation film as a portion thereof. A third conductive layer is surrounded by the gate-insulating film.

摘要翻译： 在半导体衬底上方形成绝缘膜。 第一导电层形成在电介质膜中并沿第一方向延伸。 第一导电层连接到第一选择晶体管。 形成在电介质膜中并沿第一方向延伸的第二导电层。 第二导电层连接到第二选择晶体管。 半导体层连接到第一和第二导电层两者并用作存储晶体管的沟道层。 在半导体层上形成栅极绝缘膜。 栅极绝缘膜包括作为其一部分的电荷累积膜。 第三导电层被栅极绝缘膜包围。