Invention Grant
US08432216B2 Data-path cell on an SeOI substrate with a back control gate beneath the insulating layer
有权
SeOI衬底上的数据通道单元,在绝缘层下面带有一个后控制栅极
- Patent Title: Data-path cell on an SeOI substrate with a back control gate beneath the insulating layer
- Patent Title (中): SeOI衬底上的数据通道单元,在绝缘层下面带有一个后控制栅极
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Application No.: US13007483Application Date: 2011-01-14
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Publication No.: US08432216B2Publication Date: 2013-04-30
- Inventor: Carlos Mazure , Richard Ferrant
- Applicant: Carlos Mazure , Richard Ferrant
- Applicant Address: FR Bernin
- Assignee: Soitec
- Current Assignee: Soitec
- Current Assignee Address: FR Bernin
- Agency: Winston & Strawn LLP
- Priority: FR1051526 20100303
- Main IPC: G05F1/10
- IPC: G05F1/10 ; H01L27/105 ; G06F17/50

Abstract:
The invention provides a data-path cell specifically adapted to its environment for use in an integrated circuit produced on a semiconductor-on-insulator (SeOI) substrate. The data-path cell includes an array of field-effect transistors, each transistor having a source region, a drain region and a channel region formed in the thin semiconductor layer of the SeOI substrate, and further having a front gate control region formed above the channel region. In particular, one or more transistors of the data-path cell further includes a back gate control region formed in the bulk substrate beneath the channel region and configured so as to modify the performance characteristics of the transistor in dependence on its state of bias. Also, an integrated circuit including one or more of the data-path cells and methods for designing or driving these data-path cells.
Public/Granted literature
- US20110215860A1 DATA-PATH CELL ON AN SeOI SUBSTRATE WITH A BACK CONTROL GATE BENEATH THE INSULATING LAYER Public/Granted day:2011-09-08
Information query
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