公开(公告)号：US08575697B2

公开(公告)日：2013-11-05

申请号：US13039167

申请日：2011-03-02

申请人： Carlos Mazure ,  Richard Ferrant ,  Bich-Yen Nguyen

发明人： Carlos Mazure ,  Richard Ferrant ,  Bich-Yen Nguyen

IPC分类号： H01L27/11 ,  H01L27/12 ,  G11C5/06 ,  G11C11/00

CPC分类号： H01L27/1104 ,  G11C11/412 ,  H01L21/84 ,  H01L27/1203

摘要： An SRAM-type memory cell that includes a semiconductor on insulator substrate having a thin film of semiconductor material separated from a base substrate by an insulating layer; and six transistors such as two access transistors, two conduction transistors and two charge transistors arranged so as to form with the conduction transistors two back-coupled inverters. Each of the transistors has a back control gate formed in the base substrate below the channel and able to be biased in order to modulate the threshold voltage of the transistor, with a first back gate line connecting the back control gates of the access transistors to a first potential and a second back gate line connecting the back control gates of the conduction transistors and charge transistors to a second potential. The first and second potentials can be modulated according to the type of cell control operation.

摘要翻译： 一种SRAM型存储单元，包括绝缘体上半导体衬底，其具有通过绝缘层从基底衬底分离的半导体材料薄膜; 以及六个晶体管，例如两个存取晶体管，两个导通晶体管和两个电荷晶体管，其布置成与导通晶体管形成两个反向耦合的反相器。 每个晶体管具有形成在通道下方的基底衬底中的后控制栅极，并且能够被偏置以便调制晶体管的阈值电压，第一背栅极线将存取晶体管的背控制栅极连接到 第一电位和第二背栅极线，其将导通晶体管和电荷晶体管的背控制栅极连接到第二电位。 第一和第二电位可以根据电池控制操作的类型进行调制。

公开(公告)号：US08432216B2

公开(公告)日：2013-04-30

申请号：US13007483

申请日：2011-01-14

申请人： Carlos Mazure ,  Richard Ferrant

发明人： Carlos Mazure ,  Richard Ferrant

IPC分类号： G05F1/10 ,  H01L27/105 ,  G06F17/50

CPC分类号： H01L27/1203 ,  H01L29/78609 ,  H01L29/78648

摘要： The invention provides a data-path cell specifically adapted to its environment for use in an integrated circuit produced on a semiconductor-on-insulator (SeOI) substrate. The data-path cell includes an array of field-effect transistors, each transistor having a source region, a drain region and a channel region formed in the thin semiconductor layer of the SeOI substrate, and further having a front gate control region formed above the channel region. In particular, one or more transistors of the data-path cell further includes a back gate control region formed in the bulk substrate beneath the channel region and configured so as to modify the performance characteristics of the transistor in dependence on its state of bias. Also, an integrated circuit including one or more of the data-path cells and methods for designing or driving these data-path cells.

摘要翻译： 本发明提供一种特别适用于其环境的数据通道单元，用于在绝缘体上半导体（SeOI）衬底上制造的集成电路中。 数据通道单元包括场效应晶体管阵列，每个晶体管具有形成在SeOI衬底的薄半导体层中的源极区，漏极区和沟道区，并且还具有形成在栅极上的前栅极控制区 渠道区域。 特别地，数据通道单元的一个或多个晶体管还包括形成在沟道区下面的体衬底中的背栅极控制区域，并且被配置为根据其偏置状态来修改晶体管的性能特性。 而且，包括一个或多个数据路径单元的集成电路以及用于设计或驱动这些数据路径单元的方法。

公开(公告)号：US08305803B2

公开(公告)日：2012-11-06

申请号：US12942754

申请日：2010-11-09

申请人： Carlos Mazure ,  Richard Ferrant

发明人： Carlos Mazure ,  Richard Ferrant

IPC分类号： G11C11/40 ,  G11C11/402

CPC分类号： H01L29/7841 ,  G11C11/404 ,  G11C2211/4016 ,  H01L27/0711 ,  H01L27/10802 ,  H01L29/086 ,  H01L29/7302

摘要： The invention relates to a memory cell having an FET transistor with a source, a drain and a floating body between the source and the drain, and an injector that can be controlled to inject a charge into the floating body of the FET transistor. The injector includes a bipolar transistor having an emitter, a base and a collector formed by the body of the FET transistor. Specifically, in the memory cell, the emitter of the bipolar transistor is arranged so that the source of the FET transistor serves as the base for the bipolar transistor. The invention also includes a memory array comprising a plurality of memory cells according to the first aspect of the invention, and to methods of controlling such memory cells.

摘要翻译： 本发明涉及具有源极，漏极和源极和漏极之间的浮体的FET晶体管的存储单元，以及可以被控制以将电荷注入到FET晶体管的浮动体中的注入器。 注射器包括具有由FET晶体管的主体形成的发射极，基极和集电极的双极晶体管。 具体地说，在存储单元中，双极型晶体管的发射极配置成使FET晶体管的源极作为双极晶体管的基极。 本发明还包括包括根据本发明的第一方面的多个存储器单元的存储器阵列以及控制这种存储器单元的方法。

公开(公告)号：US20110241157A1

公开(公告)日：2011-10-06

申请号：US12793515

申请日：2010-06-03

申请人： Carlos Mazure ,  Richard Ferrant ,  Konstantin Bourdelle ,  Bich-Yen Nguyen

发明人： Carlos Mazure ,  Richard Ferrant ,  Konstantin Bourdelle ,  Bich-Yen Nguyen

IPC分类号： H01L21/762 ,  H01L29/02

CPC分类号： H01L21/76254 ,  H01L21/187 ,  H01L21/2007 ,  H01L21/76251

摘要： The invention relates to a method for manufacturing a semiconductor substrate, in particular a semiconductor-on-insulator substrate by providing a donor substrate and a handle substrate, forming a pattern of one or more doped regions typically inside the handle substrate, and then attaching such as by molecular bonding the donor and the handle substrate to obtain a donor-handle compound.

摘要翻译： 本发明涉及一种制造半导体衬底，特别是绝缘体上半导体衬底的方法，该衬底通过提供施主衬底和处理衬底，形成典型地在手柄衬底内的一个或多个掺杂区域的图案， 通过分子键合供体和手柄底物以获得供体 - 处理化合物。

公开(公告)号：US20110133822A1

公开(公告)日：2011-06-09

申请号：US13013580

申请日：2011-01-25

申请人： Carlos Mazure ,  Richard Ferrant

发明人： Carlos Mazure ,  Richard Ferrant

IPC分类号： G05F1/10 ,  H01L27/105 ,  G06F17/50

CPC分类号： H01L21/84 ,  H01L27/0207 ,  H01L27/11807 ,  H01L27/1203

摘要： This invention provides a semiconductor device structure formed on a conventional semiconductor-on-insulator (SeOI) substrate defined by a pattern defining at least one field-effect transistor having: in the thin film of the SeOI substrate, a source region, a drain region, a channel region, and a front control gate region formed above the channel region; and in the base substrate beneath the buried oxide of the SeOI substrate, a back control gate region, arranged under the channel region and configured to shift the threshold voltage of the transistor in response to bias voltages. This invention also provides patterns defining standard-cell-type circuit structures and data-path-cell type circuit structures that include arrays of the FET patterns provided by this invention. Such circuit structures also include back gate lines connecting the back gate control regions. This invention also provides methods of operating and designing such semiconductor device structures.

摘要翻译： 本发明提供了一种半导体器件结构，其形成在传统的绝缘体上半导体（SeOI）衬底上，该衬底由限定至少一个场效应晶体管的图案限定，该场效应晶体管具有：在SeOI衬底的薄膜中，源极区， ，沟道区和形成在沟道区上方的前控制栅区; 以及位于所述SeOI衬底的所述掩埋氧化物之下的所述基底衬底中，所述背面控制栅极区域布置在所述沟道区域下方并且被配置为响应于偏压而移位所述晶体管的阈值电压。 本发明还提供了定义包括由本发明提供的FET图案的阵列的标准单元型电路结构和数据路径单元型电路结构的图案。 这种电路结构还包括连接背栅极控制区域的后栅极线。 本发明还提供了操作和设计这种半导体器件结构的方法。

公开(公告)号：US09490264B2

公开(公告)日：2016-11-08

申请号：US12984466

申请日：2011-01-04

申请人： Carlos Mazure ,  Richard Ferrant

发明人： Carlos Mazure ,  Richard Ferrant

IPC分类号： H01L21/331 ,  H01L21/8222 ,  H01L27/12 ,  H01L21/74 ,  H01L21/84 ,  H01L27/108 ,  H01L29/732 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L27/1203 ,  H01L21/743 ,  H01L21/84 ,  H01L27/10802 ,  H01L27/10873 ,  H01L29/732 ,  H01L29/7841 ,  H01L29/78639

摘要： The invention relates to a semiconductor device produced on a semiconductor-on-insulator substrate that includes a thin layer of semiconductor material separated from a base substrate by a buried insulating layer, the device including a first conducting region in the thin layer, a second conducting region in the base substrate and a contact connecting the first region to the second region through the insulating layer. The invention also relates to a process for fabricating such semiconductor devices.

摘要翻译： 本发明涉及一种在绝缘体上半导体衬底上制造的半导体器件，其包括通过掩埋绝缘层与基底衬底分离的半导体材料的薄层，该器件包括薄层中的第一导电区域，第二导电层 区域和通过绝缘层将第一区域连接到第二区域的接触。 本发明还涉及制造这种半导体器件的方法。

公开(公告)号：US09159400B2

公开(公告)日：2015-10-13

申请号：US13422697

申请日：2012-03-16

申请人： Richard Ferrant ,  Gerhard Enders ,  Carlos Mazure

发明人： Richard Ferrant ,  Gerhard Enders ,  Carlos Mazure

IPC分类号： G11C7/06 ,  G11C11/4091 ,  G11C11/4097

CPC分类号： G11C11/4091 ,  G11C7/065 ,  G11C11/4097

摘要： A semiconductor memory having bit lines and wordlines crossing each other, a memory cell array formed by memory cells arranged in rows and columns on crossover points of the bit lines and wordlines, and sense amplifier banks arranged on opposite sides of the memory cell array. Each sense amplifier bank has staggered sense amplifiers connected to a bit line according to an interleaved arrangement whereby bit lines alternate in the direction of the wordlines between bit lines coupled to different sense amplifiers. This results in interconnect spaces parallel to the bit lines. Also, each sense amplifier bank includes a local column decoder for selecting a sense amplifier and which is staggered with the sense amplifiers and coupled to the sense amplifier by an output line running in an available interconnect space parallel to the bit lines.

摘要翻译： 具有彼此交叉的位线和字线的半导体存储器，由位线和字线的交叉点上以列和列排列的存储单元形成的存储单元阵列以及布置在存储单元阵列的相对侧上的读出放大器组。 每个读出放大器组具有根据交错布置连接到位线的交错读出放大器，由此位线在耦合到不同读出放大器的位线之间的字线方向上交替。 这导致互连空间与位线平行。 此外，每个读出放大器组包括本地列解码器，用于选择读出放大器，并与读出放大器交错，并通过在平行于位线的可用互连空间中运行的输出线耦合到读出放大器。

公开(公告)号：US08654602B2

公开(公告)日：2014-02-18

申请号：US13495632

申请日：2012-06-13

申请人： Carlos Mazure ,  Richard Ferrant ,  Bich-Yen Nguyen

发明人： Carlos Mazure ,  Richard Ferrant ,  Bich-Yen Nguyen

IPC分类号： G11C8/00

CPC分类号： G11C8/08 ,  G11C11/4085 ,  G11C2211/4016

摘要： A circuit made on a semiconductor-on-insulator substrate. The circuit includes a first transistor having a first channel, a second transistor having a second channel, with the transistors provided in serial association between first and second terminals for applying a power supply potential, each of the transistors comprising a drain region and a source region in the thin layer, a channel extending between the source region and the drain region, and a front control gate located above the channel. Each transistor has a back control gate formed in the base substrate below the channel of the transistor and capable of being biased in order to modulate the threshold voltage of the transistor. At least one of the transistors is configured for operating in a depletion mode under the action of a back gate signal which will sufficiently modulate its threshold voltage.

摘要翻译： 在绝缘体上半导体衬底上制成的电路。 该电路包括具有第一通道的第一晶体管，具有第二通道的第二晶体管，晶体管以第一和第二端子串联连接的方式提供，以施加电源电位，每个晶体管包括漏极区域和源极区域 在薄层中，在源极区域和漏极区域之间延伸的沟道以及位于沟道上方的前部控制栅极。 每个晶体管具有形成在晶体管的沟道下方的基底衬底中的背控制栅极，并且能够被偏置以便调制晶体管的阈值电压。 晶体管中的至少一个被配置为在充分调制其阈值电压的背栅信号的作用下以耗尽模式工作。

公开(公告)号：US08508289B2

公开(公告)日：2013-08-13

申请号：US13013580

申请日：2011-01-25

申请人： Carlos Mazure ,  Richard Ferrant

发明人： Carlos Mazure ,  Richard Ferrant

IPC分类号： G05F1/10 ,  H01L27/105 ,  G06F17/50

CPC分类号： H01L21/84 ,  H01L27/0207 ,  H01L27/11807 ,  H01L27/1203

摘要： This invention provides a semiconductor device structure formed on a conventional semiconductor-on-insulator (SeOI) substrate defined by a pattern defining at least one field-effect transistor having: in the thin film of the SeOI substrate, a source region, a drain region, a channel region, and a front control gate region formed above the channel region; and in the base substrate beneath the buried oxide of the SeOI substrate, a back control gate region, arranged under the channel region and configured to shift the threshold voltage of the transistor in response to bias voltages. This invention also provides patterns defining standard-cell-type circuit structures and data-path-cell type circuit structures that include arrays of the FET patterns provided by this invention. Such circuit structures also include back gate lines connecting the back gate control regions. This invention also provides methods of operating and designing such semiconductor device structures.

摘要翻译： 本发明提供了一种半导体器件结构，其形成在传统的绝缘体上半导体（SeOI）衬底上，该衬底由限定至少一个场效应晶体管的图案限定，该场效应晶体管具有：在SeOI衬底的薄膜中，源极区， ，沟道区和形成在沟道区上方的前控制栅区; 以及位于所述SeOI衬底的所述掩埋氧化物之下的所述基底衬底中，所述背面控制栅极区域布置在所述沟道区域下方并且被配置为响应于偏压而移位所述晶体管的阈值电压。 本发明还提供了定义包括由本发明提供的FET图案的阵列的标准单元型电路结构和数据路径单元型电路结构的图案。 这种电路结构还包括连接背栅极控制区域的后栅极线。 本发明还提供了操作和设计这种半导体器件结构的方法。

公开(公告)号：US20110242926A1

公开(公告)日：2011-10-06

申请号：US12793553

申请日：2010-06-03

申请人： Carlos Mazure ,  Richard Ferrant ,  Bich-Yen Nguyen

发明人： Carlos Mazure ,  Richard Ferrant ,  Bich-Yen Nguyen

IPC分类号： G11C8/08 ,  G05F1/10

CPC分类号： G11C8/08 ,  G11C11/4085 ,  G11C2211/4016

摘要： A circuit made on a semiconductor-on-insulator substrate. The circuit includes a first transistor having a first channel, a second transistor having a second channel, with the transistors provided in serial association between first and second terminals for applying a power supply potential, each of the transistors comprising a drain region and a source region in the thin layer, a channel extending between the source region and the drain region, and a front control gate located above the channel. Each transistor has a back control gate formed in the base substrate below the channel of the transistor and capable of being biased in order to modulate the threshold voltage of the transistor. At least one of the transistors is configured for operating in a depletion mode under the action of a back gate signal which will sufficiently modulate its threshold voltage.

摘要翻译： 在绝缘体上半导体衬底上制成的电路。 该电路包括具有第一通道的第一晶体管，具有第二通道的第二晶体管，晶体管以第一和第二端子串联连接的方式提供，以施加电源电位，每个晶体管包括漏极区域和源极区域 在薄层中，在源极区域和漏极区域之间延伸的沟道以及位于沟道上方的前部控制栅极。 每个晶体管具有形成在晶体管的沟道下方的基底衬底中的背控制栅极，并且能够被偏置以便调制晶体管的阈值电压。 晶体管中的至少一个被配置为在充分调制其阈值电压的背栅信号的作用下以耗尽模式工作。