发明授权
US08435802B2 Conductor layout technique to reduce stress-induced void formations
有权
导体布置技术,以减少应力引起的空隙形成
- 专利标题: Conductor layout technique to reduce stress-induced void formations
- 专利标题(中): 导体布置技术,以减少应力引起的空隙形成
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申请号: US11438127申请日: 2006-05-22
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公开(公告)号: US08435802B2公开(公告)日: 2013-05-07
- 发明人: Min-Hwa Chi , Tai-Chun Huang , Chih-Hsiang Yao
- 申请人: Min-Hwa Chi , Tai-Chun Huang , Chih-Hsiang Yao
- 申请人地址: TW Hsin-Chu
- 专利权人: Taiwan Semiconductor Manufacturing Co., Ltd.
- 当前专利权人: Taiwan Semiconductor Manufacturing Co., Ltd.
- 当前专利权人地址: TW Hsin-Chu
- 主分类号: H01L21/00
- IPC分类号: H01L21/00
摘要:
A semiconductor device is prepared by an annealing process to interconnect at least two components of the device by a conductor line surrounded by an insulator material. The annealing process results in formation of residual stresses within the conductor line and the insulator material. A notch is designed in the layout on a selective portion of the mask for patterning conductor line. The existence of a shape of notch on the selective portion generates extra stress components within the conductor line than if without the existence of the notch. The position of the notch is selected so that the extra stress components substantially counteract the residual stresses, thereby causing a net reduction in the residual stresses. The reduction in the residual stresses results in a corresponding mechanical stress migration and therefore improvement in the reliability of the device.
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